We use a T.I. PHY DP83867ERGZT connected to FPGA Microsemi through SGMII and SMI (MDIO).
We do not have the same behavior after power-on reset and after hard reset on pin RESET:
- After power-on reset, the PHY works correctly
- After hard reset, the PHY does not answer from MDIO and no communication on Ethernet
In both cases, the FPGA generates a 3µs low pulse on RESET_N pin of the PHY, then accesses to MDIO when requested by SW (after >5s).
During and after (power-on or hard) reset , until configuration is requested from SW:
- MDC is fixed to logical 0 (then 2.5MHz during SW configuration)
- MDIO is pull-up to logical 1
After reading T.I forum and datasheet, I understand that we have to generate 32 extra MDC cycle with no data (MDIO=1) after reset and before MDIO access.
So we tested this configuration after power-on and hard reset.
No improvement was detected: still OK after power-on reset, and KO after hard reset as before.
We tested "manual" reset by pulling-down the RESET_N signal with a probe (during 200ms-1s approx) after PHY hang and MDIO access is granted and PHY works again afterwards!
We modified the FPGA configuration to generate 3ms low pulse RESET_N (i.e. x1000 duration) after power-on or hard reset and the PHY does not hang anymore.
But we do not explain this behavior as the datasheet only requires 1µs low pulse on RESET_N.
Could you please explain what could be wrong in our sequence ?
Thanks and Best regards.
Emmanuel
