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Unused inputs and Outputs on SN65LBC174A-EP and SN65LBC173

Other Parts Discussed in Thread: SN65LBC174A-EP, SN65LBC173, SN74LVCH244A, SN65LBC174A

Looking for guidance as to what to do with the unused inputs and outputs on these devices:

SN65LBC174A-EP and SN65LBC173

I am also using a SN74LVCH244A, however the datasheet states that it's ok to leave these inputs floating due to the bus-hold circuitry?

 

  • 1) SN74LVCH244A : the data sheet states not to use external pull-up/down resistors with this device due to its internal bus hold circuitry. What is not clear with this advice?

    2) SN65LBC174A : while the logic inputs A and EN have internal 100k pull-ups, I always recoomend adding external 4.7k pull-up resistors when operating in noise environment.

    3) SN65LBC173 : here the data sheet states that the device includes open-circuit failsafe circuitry. Whenever you unused receiver pins or you operate without termination resistors (due to short bus length or low data rate) an internal circuitry will generate enough differential voltage at the bus input terminals to switch the receiver outputs into a logic HIGH output state.

    However, when using termination resistors and your drivers on the other end of the bus go high-impedance, then the low-impedance termination resistor (of 100 or 120 ohms) connects the differential inputs and the differential input voltage drops below the internal failsafe threshold. In this case you will need external biasing resistors which pull-up the non-inverting receiver input to Vcc and the inverting input to ground. Because these resistors create a volatge divider with the termination resistor, they must be low-impedance enough to cause a voltage drop of at least 200mV plus whatever you expect on noise voltage.

    Example: If your Vcc = 5V +/- 5%, your termination resistor Rt = 120 ohms, and your expected noise voltage, Vn = 50mV, then simply add the 50mV to the internal receiver threshold of Vth = 200mV. The total differential input voltage of Vid = 250mV during bus-idling must drop across the termination resistor, and also under minimum supply conditios,so when Vcc-min = 4.75V.

    With 0.25V dropping across the termination resistor there are only 4.75V - 0.25V = 4.5V left for the two biasing resistors, or 2.25V for each biasing resistor, Rb. Now simply write the relation Rb / Rt = 2.25V / 0.25V and solve for Rb. This yields: Rb = Rt x 2.25V / 0.25V, or Rb = 9 x Rt.

    Thus for Rt = 120 ohms, make each Rb = 9 x 120 ohms = 1080 ohms. Choose the next 1% resistor value from the E192 series with Rb = 1.07k.

    Note, each receiver in use should have a biasing network of a 1.07k pull-up and a 1.07k pull down-resistor.

    But please recall, unused receivers and receivers without termination can rely on the device internal failsafe circuitry and do not require an external bisaing network.

    I hope this claryfies it a little.

    regards, Thomas 

     

  • Thomas,

    Please pardon the breadth of my questions, as I am a new designer in the industry.

    The environment will be very noisy, so I guess I will go with the approach of putting 4.7k pull ups on the Logic A and EN inputs of the SN65LBC174A's.  Does it matter if the inputs are attached to an FPGA? Would the pull up still be required and would the value of the pull up change?

     

    What is the implication of not using biasing resistors on the SN65LBC173? Is this to ensure the input sensitivity remains above 200mV, so that the output is not indeterminate when the driving side is high impedance?  What is the general concept, when the drivers are high impedance, the receivers should keep the prior value? 

    Thanks

  • Thomas,

    I think I'll go with the triple protection scheme as stated in the Interface Circuits for TIA/EIA-485 (RS-485) app note I found on the TI web site. However, I will use R1 = 2K, as opposed to 2.5K as they show in the example. Using 2K will give me about 60mV more margin.  Let me know what you think.

  • You a new designer? Are you kidding?

    you are asking the questions of a pro. Don't you worry there many older engineers, who think they have seen it all (including me) but we are still learning on a daily base. Industrial application have always some little surprises for you in petto, mostly when and where you do not expect them.

    With regards to to pull-ups, this advice was only for floating Logic and Enable inputs (and of course inputs driven by open-drain or open-collector outputs). If they are connected to FPGA outputs, with push-pull structure then the pull-ups are not required.

    There is no implication for NOT using external biasing resistors. There is an implication IF you do use them. The internal circuitry is so designed that there is already a certain biasing, which will be reduced by external components.

    The general concept when driver outputs are high impedance is to avoid floating inputs at the receiver inputs on the other end of the data link. Because receiver inputs are usually high-impedance, small noise signals could potentially cross the internal receiver input thresholds (in both directions) causing the receiver output to toggle. Thus the general concept is to bias the inputs so that the outputs are in a defined logic state (High OR Low does not matter). In RS-485 transceiver for example, most receiver outputs assume logic High if their inputs are disconnect, or the bus line is idle.

    Regards,

    Thomas 

     

     

  • Sounds good to me. Let me know how it works. By the way we have a ton of other application notes on the subject too. Search our side and if you don't find a certain topic let me know. Either I know where to find it or I can write a new apps-note about it.

    Now good luck with your design.

    Thomas

  • Thomas,

    I also took into consideration the following information on whether or not a termination resistor is actually required.

    http://www.bb-elec.com/tech_articles/rs422_485_app_note/system_configuration.asp

     

    For my particular design I actually determined it isn't necessary according to the guidelines. However, if I don't create my own failsafes, then I will be purely relying on the device's failsafe capability, which according to the datasheet, only provides Open-Circuit failsafe.  If I don't use a termination resistor, can I expand the open-circuit failsafe to include short circuit and idle conditions?

    For example, in referencing the TI app note Interface Circuits for TIA/EIA-485 (RS-485), Figure 7 shows a 120 ohm termination resistor. Do you think I will be able to design to the constraints recommended in the app note purely by just eliminating R2 in the formulas?

     

     

  • since you don't care about termination your only design constraints is that for short circuit:

    Vcc x R3 / (R1+R3) > 200mV,

    or solving for R3:

    R3 > R1 x 200mV / (Vcc - 200mV)

     regards, Thomas