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Original question:

DS90UB941AS-Q1: how to configure to drive 2 independent touch screen

DS90UB941AS-Q1: configure to drive 2 independent touch screen, the PORT1 logical status of the interrupt is inconsistent with that described in the manual

user6105554
Prodigy 151 points
Part Number: DS90UB941AS-Q1

Hello team:

  Currently we have a product solution that use 1 941 to connect 2 948, to drive 2 screens and each one has touch.

According to https://www.ti.com/lit/an/snla308a/snla308a.pdf,  Figure 10-4. INTB Logic in Splitter Interrupt Mode

we need reading the isr(0xC7) to clearded to high;

In fact, we didn't do anything,but the interrupt automatically increases, and the interrupt logic is consistent with port0;

The following are the actual measurement results of the logic analyzer

For the 941 in splitter mode:

we Set SER register 0x30=0x01; and 0xC6=0x01;  

In fact, with this setup, two independent TP can already work properly;

but, we Set SER register 0x30=0x01; and 0xC6=0x21;  

then,touch the screen , the port1 intb pin we got nothing; as shown in the following figure

Is there any mistake in our understanding of the document? The behavior of the interrupt was not consistent with the manual documentation, so we were confused?

could you please support this issue?

  • 0
    TI__Mastermind 22965 points

    Hi Zheng,

    Is INTB on the 941AS pulled high to VDD? On both of the logic screenshots, INTB is kept low by default when it should be pulled high by default. 

    Best,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 151 points
    in fact, our hardware is completely based on the design of Figure 10-2 Interrupt Propagation in Splitter Mode Block Diagram

    INTB on the 941AS pulled high to VDD;    If register 0x30 is not set, INTB is kept hight by default 

    when  set 941AS,register 0x30 =0x00 and 0xc6= 0x21;then,touch screen

    Read port1 0xc7,   intb  clearded to high;

    At this point, set register 0x30 to 0x01 ，intb automatically pulls down。as shown below

    There any other register  configurations we're missing?

  • 0 in reply to user6105554
    TI__Mastermind 22965 points

    Hi Zheng,

    For the INTB pin, this pin is sensitive to interrupts from devices on both TX ports depending on how register 0xC6 is configured. The app note states

    The HDCP_ICR register is the same as 0xC6 is the UB941AS.

    user6105554 said:

    but, we Set SER register 0x30=0x01; and 0xC6=0x21;  

    then,touch the screen , the port1 intb pin we got nothing; as shown in the following figure

    INTB is kept low because it was not allowed to clear. If 0xC6=0x21, the INTB pin will react to INTB_IN from both deserializers on port 0 and port 1. INTB_IN must be kept low on both deserializers to allow INTB to clear.

    Make sure that when 0xC6=0x21 that INTB_IN on both deserializers is not active when reading 0xC7 or INTB will not reset.

    Best,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 151 points

    I know that situation, 

    In fact, reading register 0xc7 manually that does clear intb to hight，at this time, the interrupt service is triggered, the TP coordinates are read, and INTB_IN is released to the high state;

    Therefore, the interrupt service function cannot be configured to trigger the falling edge, and the INTB state cannot be cleared to high  by  the  interrupt service

    Trigger mode of screen TP interrupt;

    Can we understand that this screen is not suitable for documentation describing interrupt logic in split screen mode?

     

    Finally, configure registers 0x30=0x01 and 0xc6=0x01; the port1 th INTB pin on the 941AS output the opposite logic level of INTB_IN automatically;

    Is this a normal phenomenon and it can  be used in this way?

  • 0 in reply to user6105554
    TI__Mastermind 22965 points

    Hi Zheng,

    user6105554 said:
    Is this a normal phenomenon and it can  be used in this way?

    This is not a normal phenomenon. I can see that REM_INTB is held low which indicates that INTB_IN on Port 0 is held low. Because 0xC6 = 0x01, there is possibly a conflict with Port 0 and Port 1 interrupts. Does this behavior stay the same with 0xC6=0x0?

    As depicted in the diagram, the INTB pin is affect by the interrupt from Port 0. 

    Best,

    Jack

  • 0 in reply to Jack Scherlag
    TI__Mastermind 22965 points

    Hi Zheng,

    To follow up, register 0xC7 will need to be read whenever a global interrupt is detected in order to clear INTB. If 0xC7 has not been read and a new interrupt from Port 1 is triggered, INTB will not be able to react properly.

    Best,

    Jack