DP83825I: sensible to indirect ESD

Hi Hanno,

Can you clarify what type of indirect ESD is being introduced?

I can help provide suggestions if the conditions for chip failure are clarified.

Thank you,

Evan

Hi Evan,

we have an aluminium plate with earth potential which is mounted to the four corners of the platine with the DP83825I. Aluminium plate and the platine are parallel. The distance between aluminium plate and platine is 3mm but tests showed that the distance does not make any difference. When we give a +/- 8kv esd of shot to the aluminium plate the DP83825I gets a reset. The registers in the IC get their reset values and we have to configure it again. We do not think that there is any problem with the 3,3V supply because other ICs supplied with 3,3V do not have any problems. The reset line has 1000 Ohm resistance in row and a capacity with 68pf very close to the reset pin of the chip. We use also the DP83822I on the same platine without any problems. The circuit(schematic) is the same like in the evaluation board DP83825EVM.

Thank you,
Salim

Hi Salim,

Thank you for clarifying. I have some more questions for the team to help diagnose root cause:

[1] How is the internal config reset being measured? Which registers are changing after ESD strike?

[2] Can the schematic/layout be shared?

[3] How has stable power/reset been verified during ESD strike? Can scope-shots of power and reset lines be shared during ESD test?

I'm not aware of any conditions for PHY reset independent from the power and reset lines, so it would be helpful to confirm these are not the cause.

Thank you,

Evan

Hi Evan,

thank you for replying.

to [1]:

we are disabling auto negotiation in the BMCR register and never setting it back to auto negotiation again. After giving an esd to the aluminum plate the ethernet communication of the DP83825i phy stops and when we read the Auto-Negotiation_Enable bit of the BMCR register we see that it is back to the reset value and auto negotiation is active again.

to [2]:

I will attach the schematic and the layout. The platine is built like in the pictures atached. After we noticed the problem with esd we modified the platine
Relevant modifications I made:
-Added a coil for VDDIO(pin19)
-Added TVS and ESD diodes like in the evaluation board.
-Connected INT/PWR_DOWN with a 2,49k resistance in row to 3,3V
-the reset pin is controlled through the FPGA on the platine. I added a 1k resistance in row to the reset line and a 68pf capacity parallel to the 1nf capacity.

to [3]:

We have no meaningful scope shots during esd strike. The FPGA, the CPU and the other phy DP83822 on the platine have also the same 3,3V supply and they are not getting a reset. So the supply can not be the problem. Both capacitys on the reset line are placed very close to the pin. There is also a 1k Ohm resistance in row.

Thank you,
Salim

overview with filled polygons

overview with unfilled polygons

Hi Salim,

Thanks for sharing more details and the schematic/layout snapshots. If testing with less than 8kV ESD indirect strike (2-4kV), do you see the same register reset?

I agree that the power line should be stable if the other devices on the shared rail are not affected. The reset pin stability is still not clear to me, is it possible to capture a scope-shot of this during the strike?

I will wait for schematic/layout files (email to e-mayhew@ti.com for private share).

Thank you,

Evan

Hi Evan,

thank you for replying.

Yes it also happens with less Voltage. I tried 5kV before but not 4kV or 2kV. The same register resets. During an ESD it is not possible to make a meaningful scope shot. The probe also triggers when it is not connected to any pin. Before I send you the schematic and the layout I would ask a question.

On our layout the thermal pad of the IC is not connected to any potential. There is no information about the potential of the thermal pad in the data sheet so we left it open. But it in the evaluation board we see that the thermal pad is connected to ground potential. Could this be an explanation of this behavior ?

Thank you,
Salim

Hi Salim,

Interesting that this happens at 5kV... I suspect there is some weakness in the layout that is causing variation on power/reset during strike.

Do you have any way to further isolate the reset and power pins during ESD strike?

I'm not aware of the thermal pad being a factor in this, but I will check further with the team.

Thank you,

Evan

Hi Evan,

I will check if there is any way to isolate the reset and power pin. Could you find anything about the potential of the thermal Pad?

Thank you,
Salim

Hi Salim,

Although we have not seen or validated EMC performance with a disconnected DAP, I am thinking the weak ground path during ESD strike is a factor here.

Do you have a way to test with a better ground connection on the PAD? If the layer below the PHY's top layer happens to be ground, can the top layer be etched out for a makeshift ground plane?

Thank you,

Evan