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DS125DF1610EVM: PRBS generator loopback to PRBS checker test

Wendy Wang
Prodigy 20 points
Part Number: DS125DF1610EVM
Other Parts Discussed in Thread: DS125DF1610

I am trying to set up the loopback test to verify the BERT feature of DS125DF1610EVM. But I am having difficulty to make it work. I wonder if there is any reference guide to do this loopback test. Below are the steps I have done:

1) I powered up the EVM board and connected it PC with USB and loaded the configuration for DS125DF1610. SIgCon Arch shows the board is connected. REF_CLK is set to 312.5 MHz.

2) Use SMA2SMA cables to Connect TX_4A_P/N to RX_4B_P/N.

3) On SigCon Arch, at channel select, select RX/TX_4A, then go to PRBS Gen/Checker tab, select PRBS31 then click Enable. click "apply to channel"

4) The channel indicators shows "No signal", "CDR unlocked" 

It seems like the PRBS31 is not generated for TX_4A ports. and also not detected on RX_4B ports.

I also did another test. Use SMA2SMA cables to connect TX_4A_P/N to RX_4A_P/N (instead of RX_4B_P/N). Then enabled the PRBS31 on RX/TX_4A. I can see "signal detected". But I cannot get CDR to lock. Also on the user guide, it states "the PRBS generator and PRBS checker should be operated from different channels". I am really confused on how to set this loopback test.

Best,

Wendy

  • 0
    TI__Mastermind 27117 points

    Hi Wendy,

    The DS125DF1610 requires CDR lock in order to use the PRBS generator since the clock for the PRBS generator is sourced from the CDR recovered clock.

    This means that you must have a valid input on the RX of DS125DF1610 in order to use the PRBS generator.

    If you don't have a data at the target rate available, you can use a sub-rate clock input.  For example. for 10.3125 Gbps data, use a (10.3125 / 16) = 644.53125 MHz clock.

    Please see the E2E thread below for more details on the configuration.

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/796045/faq-ds125df1610-how-to-setup-the-device-to-generate-different-prbs-pattern?tisearch=e2e-sitesearch&keymatch=ds125df1610%2525252525252520prbs%2525252525252520faq#

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 20 points

    Hi Drew,

    Thank you for your prompt support!

    I am a little confused on how to understand the configuration in the link you posted. 

    1) Does "RAW" mean "read after write" in the script below? In the first line, is 01 the value to write 03 is the value readback? or the other way around? Can you explain why write 01 to register FF will read back 03? 

    RAW FF 01 03 //enable channel registers
    RAW FC 01 FF //select rxa0/txa0 quad 0 channel 0
    RAW FD 00 FF 

    2) In the user guide, for "scripting tab", the script format for setting registers is different from the above lines. Which one should I use?

    3) Also from low level tab, we can load or save configuration. I tried to save the configuration. The config file format also differs from the script in the link you posted. I am wondering how should I proceed. Can you send me an example of how to set up RXA4/TXA4 as shown in the link (in the link, RXA0/TXA0 is set). I would like to use RXA4/TXA4 because I have the SMA cable to connect to the SMA on the EVM board.

    Thanks,

    Wendy

  • 0 in reply to Wendy Wang
    TI__Mastermind 27117 points

    Hi Wendy,

    1) Apologies for the confusion.  In a lot of our programming guides, we use a read-modify-write (RMW) procedure.  I believe the "RAW" may be a legacy reference to this.

    For RMW procedure, there is typically the following format:

    <address> <value> <write mask>

    For example, RMW FF 01 03 would write 0x01 to address 0xFF, but only modifying bits 1 and 0 (mask=0x03).

    2) In the scripting tab, there is a way to modify specific bit fields, such as "Global Registers", "EN_CH_SMB".  If you want to use the scripting tab, I'd recommend mapping the register writes to the bit fields.

    3) After you have programmed the device (either using the low level page or scripting tab), you can save the configuration.

    What is your target data rate?  What frequency is the sub-rate clock input you're using?

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Prodigy 20 points

    Is there any documentation for how to write configuration file on low level page and how to do script for scripting tab? 

    Thanks,

    Wendy

  • 0 in reply to Drew Miller1
    Prodigy 20 points

    Hi Drew,

    I don't have anything that can output high-speed data or high-speed clock yet. I am just trying to get familiar with the BERT feature of this board. I wonder if there is any on-board clock or on-chip clock can be attached to one of the RX ports so that I can set up the device to generate the PRBS pattern?

    Wendy

  • 0 in reply to Wendy Wang
    TI__Mastermind 27117 points

    Hi Wendy,

    To write registers on the low level page:

    1) Select the appropriate register

    2) Adjust the register value by either using the check boxes for each bit, or modifying the "Data" field.

    3) Press write register to write to the register.  You can also press "broadcast" to broadcast the register setting across all channel registers.

    Note that since SigCon architect breaks the registers down into different pages on the low level page (Shared Registers, Global Registers, and Channel Registers), you do not need to do register writes specific to page selection.  For example, you can skip the writes below and instead just modify the channel registers on the desired channel (or broadcast to all channels).

    Fullscreen
    1
    2
    3
    RAW FF 01 03 //enable channel registers
    RAW FC 01 FF //select rxa0/txa0 quad 0 channel 0
    RAW FD 00 FF
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    We don't have additional documentation for the scripting tab beyond what is in the User's Guide.

    Wendy Wang said:
    I don't have anything that can output high-speed data or high-speed clock yet. I am just trying to get familiar with the BERT feature of this board. I wonder if there is any on-board clock or on-chip clock can be attached to one of the RX ports so that I can set up the device to generate the PRBS pattern?

    You could try cascading the CLK_MON (assuming it is configured for 312.5 MHz) to one of the inputs.  This would be 10 Gbps / 32.  However, dividing by 32 is a higher divider than we typically use, so I'm unsure of how effective this will be.

    If you try this, you will need the CDR set to 10 Gbps.  You can do this by writing 0xA6 to channel register 0x2F instead of 0xB6.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 20 points

    Is there any register setting that I need to write for clk_mon to be connect to ref_clk? I can measure the 312.5MHz on the ref_clk side (from one of the cap), but I don't see it at clk_mon side (I tried both the SMA connector and the cap next to it).

  • 0 in reply to Wendy Wang
    Prodigy 20 points

    According to the datasheet, I enabled the clk_mon port by setting reg 0x0A[0] to 0, and choose the undivided clcok by set reg 0x04[7] to 0. But still nothing shown up on clk_mon port. I can see 312.5MHz at ref_clk side.

  • 0 in reply to Wendy Wang
    Prodigy 20 points

    I also observed the following,

    1) ref_clk_n from on-board OSC swing from 1V to 1.4V, after ac coupling cap C349 the signal swing is from -0.2V to 0.2V.

    2) ref_clk_p from on-board OSC swing from 1V to 1.4V, after ac coupling cap C349 the signal swing is from from 0.6v -1.0v at first, then it also become from -0.2V to 0.2V.

    I hope these input can give some hint on why I am not seeing the clock_mon signals.

    Wendy

  • 0 in reply to Wendy Wang
    TI__Mastermind 27117 points

    Hi Wendy,

    I'll look into this and get back to you.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 20 points

    I got a rf function generator to generate 644.53125MHz clock and use the registers setting in the link you sent me. But no signal detected. The only thing that's different is that my function generator generate single-ended clock, I hook it to RX_P, and connect RX_N to gnd. I tried amplitude from 1dBm to 4dBm. Do you have any insights on thisj?

    Thanks,

    Wendy 

  • 0 in reply to Wendy Wang
    TI__Mastermind 27117 points

    Hi Wendy,

    Normally 400mVpp single ended would be sufficient for CDR lock.  Can you try this?  It seems strange that you aren't getting the signal detect status.

    Thanks,

    Drew