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DS280DF810: PRBS Checker

Dmitry Rozhdenko
Prodigy 65 points
Part Number: DS280DF810

There is a board for generating PRBS sequences and evaluating eye diagrams on the received channel, built on a DS280DF810 chip. Is it possible to use DS280DF810 chip, where channel Тх0 is used for PRBS generation, and channel Rx1 is used for reception of PRBS.

The transmitter and receiver of the DS280DF810 chip are connected to each other through the corresponding connectors using the loop-back module.

So will the DS280DF810 chip work, if so, what modes need to be set, if not, what needs to be changed in the scheme?

There is a DS280DF810EVM debug board, in which the Tx0 is connected to Rx1 and the Tx1 is connected to Rx0 using the cable supplied with this board. The registers for the Tx0 and Rx1 channels were configured, where the Tx0 generator is PRBS and the Rx1 is the receiver (nothing was set in the registers for the Tx1 and Rx0 channels) using the DS280DF810EVM debugging board program and an eye diagram was obtained.

If we disconnect the cable from the Tx1-> Rx0 pair, and Tx0 is connected by a cable with Rx1 the eye diagram falls apart. Why does this happen, maybe some mode is not configured?

  • 0
    TI__Guru* 93670 points
    Hi Dmitry,
    One can enable PRBS generation using an integer multiple clock or locking the device to a data stream and then enabling PRBS on that channel.

    It would help if you could please show a block diagram of what you are trying to achieve. If I understand you correctly, you have TX0 connected to RX1 and TX1 connected to RX0. Then you disconnect TX1 to RX0 and run TX0 to scope and there is no eye diagram. I think what is happening is that RX0 need a signal to generate PRBS.

    You can take a clock source and connect to RX0 and then enable RX0 channel to lock and generate PRBS pattern. In this case, you can take TX0 to scope or RX1 so RX1 channel can lock to this data.

    Please note a more detailed explanation of hos to setup the device for this operation:
    e2e.ti.com/.../701759

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Prodigy 65 points
    I want to clarify:
    At the beginning, Tx0 is connected to Rx1 and Tx1 is connected to Rx0 on the DS280DF810EVM Evaluation board by the bundled cable, the registers for the Tx0 and Rx1 channel were configured using the program for the Evaluation board DS280DF810EVM, where Tx0 is the PRBS generator and Rx1 is the receiver, and an eye chart was received but nothing was recorded in the registers for the Tx1 and Rx0 channels.
    Then a board was drawn to generate the PRBS sequence and evaluate the eye diagrams on the received channel, built on the DS280DF810 chip. There the Tx0 channel is used to generate the PRBS, and the Rx1 channel is used to receive the PRBS. The transmitter and receiver of the DS280DF810 microcircuit are connected to each other through the corresponding connectors using the loop-back module. Register settings for the DS280DF810EVM debug board were used for our board. But the eye chart could not be obtained.
    An experiment was conducted on the Evaluation board: in the version where we managed to get an eye diagram, disable the Tx1-> Rx0 pair, and Tx0 is connected to Rx1 as on our board. We apply the same register settings for the variant which I described at the beginning of the letter. At the same time, the eye diagram is falling apart.
    Why does it happen?
    Perhaps some mode is not configured?
    Or it is necessary that 2 pairs of one group (for example Tx1-> Rx0, Tx0-> Rx1) must be connected for application in the topology of one transmitter and receiver, which are in the same group?
    In Attach File shows a part of our circuit, where the number 1 shows a transmitter and a 2-receiver connected to each other through the appropriate connectors using the loop-back module.
  • 0 in reply to Dmitry Rozhdenko
    Prodigy 65 points
    How to send you a file ?
  • 0 in reply to Dmitry Rozhdenko
    TI__Mastermind 19235 points

    Hi Dmitry,

    Retimer channel 0 will not be able to output PRBS data unless there is some input data present. The basic setup/data path required is described below. A setup where retimer channel 0 Tx is fed to channel 1 Rx and channel 1 Tx is fed to channel 0 Rx is not feasible.

    • External Source Tx -> Retimer Channel 0 -> test channel -> Retimer Channel 1
    • (or) External Source Tx -> Retimer Channel 1 -> test channel -> Retimer Channel 0

    Each retimer channel is independent, as each one has its own CDR and its own set of channel registers.

    The external source Tx signal may be either a PRBS pattern or 1010 clock signal of data rate matching the CDR rate programmed on the retimer channels under test.

    Please note that TI has a software GUI available called SigCon Architect which allows you to configure the retimer EVM and also read its status registers. 

    The main updater for SigCon Architect is downloadable via link below.

    www.ti.com/.../SIGCONARCHITECT

    Download access for the DS280DF810 GUI profile can be requested via the TI.com product page.

    www.ti.com/.../DS280DF810

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer