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DS125DF1610: PRBS checker setting

Part Number: DS125DF1610

Hi,
I am able to generate PRBS signal out of QUAD1 TX channels (QUAD1 input is ref clock). I am trying to get PRBS checker working out of QUAD0 channels.
I can't get it to work, even CDR is not locked.
Please help me set PRBS checker setting correctly.

Thanks,

Kilhun

  • This is my PRBS checker settings,

  • This is my PRBS checker settings, (TEXT)


    Shared Registers        
    Data Address (D/H)    Bytes Contents    Description of field
    02h    40h    REFCLK_SEL
    FCh    04h    Channel Sel
    FFh    01h    WRITE_ALL_CH
    Channel Registers        
    Data Address (D/H)    Bytes Contents    Description of field
    09h    20h    R/W
    0Ah    58h    R/W
    0Ch    08h    R/W
    18h    00h    R/W
    1Eh    21h    R/W
    2Fh    B6h    R/W
    30h    08h    R/W
    79h    50h    R/W
    82h    9Ch    R/W
    8Dh    02h    R/W
    8Eh    3Ch    R/W
    96h    06h    R/W
    9Bh    02h    R/W

  • Hi,

    • Can you clarify the input signal type and data rate input to the quad 1 channel(s)?
    • Are you able to observe CDR locked on quad1 channel(s) for any case? PRBS generation cannot occur unless CDR is locked
    • default value for 0x0A is 0x50. Why are you setting it to 0x58? We do not recommend to keep the reset override bit asserted
    • 0x18 is being set to 0x00. Do note that manual divider settings are not effective unless 0x09[2]=1
    • I would recommend to keep the channels in normal pass-through module and not enable the crosspoint switching until this PRBS checker issue is solved

    For reference you may review the TI PRBS checker enabling routine included below.

    REG        Value    Mask     Comment

    30           00           08           //Disable PRBS clk

    0D           00           80           //Enable Deserializer

    79           00           60           //disable PRBS checker

    30           08           08           //Powerup PRBS Clk while PRBS check is disabled to clear error regs

    79           40           60           //Enable PRBS checker

     

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer