DP83869HM: Schematics Review

Hi Arijeet Saha,

For a schematic review, could you please fill out the Design Review Checklist and submit to me? It can be found on the DP83869 Product Page - Design Tools & Simulation . Upon receipt of the filled out checklist, review will take at most 5 business days.

Regards,

Alvaro

Hi Alvaro,

I am attaching the updated schematics & the checklist file for your reference. Please review & let us know your comments.

Our main concern is regarding the magnetic part we selected & whether PHY-IC supports the internal architecture.
MEDIA_CONVERTER_TI_REVIEW.pdfDP83869_Schematic_Checklist.xlsx

Hi Arijeet,

Thank you for filling out the checklist, I will complete my review by no later than Friday, June 7th.

Regards,

Alvaro

Hi Alvaro,

Sure. Please suggest on the Magnetics part if this selected MPN is unsuitable.

I have a question about link detection at the copper end. Do I also need the optical end to be detected? & vice-versa?

Hi Arijeet,

I will place the magnetic comment in the checklist.

Arijeet Saha said:

I have a question about link detection at the copper end. Do I also need the optical end to be detected? & vice-versa?

The DP83869HM has independent registers to detect copper link and fiber link. Our DP83869 Troubleshooting Guide provides more information about the behavior of these registers in Section 3.2.1 Fiber Registers.

Regards,

Alvaro

Hi Alvaro,

Please note we are designing an unmanaged switch so Troubleshooting with registers options is not feasible for us. We have only hard strapped options. 

Hi Alvaro,

Awaiting your comments.

Thanks

Arijeet 

Hi Alvaro,

Thanks a lot for the detailed review comment. We will update the same.

Any specific reason to proceed with forced 1000base-x rather than auto-negotiation?

Reg. magnetics MPN we thought to proceed with HX5012FNL. Could you please share your viewpoint on this part?

Reg. Power sequence is needed to follow the sequence shared in the datasheet. What if vddio ramps before 1V1 and 2V5?

Could you please review our power supply section (3-Supply Configuration) & comment on the sequencing logic?

We are facing a link detection issue on one of our cards. I have raised a thread. Please check and suggest if we are missing any troubleshooting steps.

e2e.ti.com/.../5238770

Hi Alvaro,

A. All comments are updated as per your review comments. 

B. Reg. Magnetics: Can you tell me how you are deciding on the internal architecture of the magnetics? HX5014 has a different internal arch. than HX5008(used in ref design) then which factors do we need to consider? HX5008 comes with a center tap after the common mode choke whereas HX5014 comes with a center tap before the common mode choke. If this is Ok means i would like to change the magnetics MPN to HX5020FNL due to space constraints.

C. Please also help share your review comments on the power section and the sequencing(logic) we are following in our design. Due to space constraints, we may need to shift to 2-power logic for our board.

D. We are looking for more optimization so, We are also not using JTAG for our design, is it ok to DNI: JTAG-TMS, CLK line components.

E. Reg. In the E2E thread, we tried forced negotiation but still nothing helped. We also tried configuring PHY in OPMODE 000. Still, we are not able to see any link on either the copper or fiber side.

Sure, please have a look and let us know the possibilities.

Hi Arijeet,

A. Good to hear

B. Aside from the Magnetic specs (return loss, insertion loss, turn ratio tolerance, etc.), I'm also checking to see if the transformer's center taps have individual connections, so that they can each get their own 0.1μF cap (see figure 1). This was mentioned in the checklist. Typically we want the CMC to be after the Transformer. 

Figure 1 -Magnetic Connection Example from Data sheet

C. Where did you provide the power sequencing logic? Forgive me if I missed it but I don't see it in the checklist. What are the power constraints of your board?

D. Yes, all JTAG pins are optional and can be left floating if not used. 

E. I will let my colleague continue handling the separate E2E thread. 

Regards,

Alvaro

Hi Alvaro,

Please share your valuable comments on the following update we are performing on our design due to space PCB- constraints

A. HX5020NL from PULSE Electronics for our application. 
B. 2-Power Supply mode is used. We are using Switcher for all the power rails & all are enabled at the same time(no seq. is followed here).
C. JTAG-TDO, and TDI are only used, the rest JTAG nets are not connected.
D. Mirror Mode is disabled, and Pass-thru is enabled.
E. Fiber is Kept in Forced Mode, Copper in Autoneg (as discussed earlier).