DP83867IS: Link Up Issue

Hi Gireesh,

Thank you for reaching out. Regarding the 5 boards, do they have this issue consistently and are the other 10 boards are not experiencing this issue at all?

Could you give more details as to what exactly is the link issue? Is it a long up time, link is never established, or unstable link? How are you checking link? Is register access always available?

How are we testing the PHY? Could you provide a block diagram of your setup and your test procedure?

Regards,

Alvaro 

Hi Alvaro,

Regarding the 5 boards, one of them was not having any issues earlier, but one day the DP83867ISRGZR suddenly failed to link up. The other 10 boards have never faced this link-up issue.

Link-Up Issue: The link is never established. The issue persists even after power cycling and resetting the boards. (However, the link comes up if the MDIO lines are accessed)

Is register access always available?: Yes, register access is always available, and we can communicate with the PHY registers without any issues. However, if we access the MDIO, the SGMII link comes up.

For testing the PHY, we are using a standard network setup. Here's a block diagram of our setup and the test procedure.

Best regards,
Gireesh

Phy.pptx

Hi Gireesh,

Have you seen our Troubleshooting Guide? Could you

1. read register 0x0-0x1E, 0x37, 0x6E, 0x6F upon boot up (with ethernet cable disconnected)
   1. See Section 2.1 & 2.7.2 in the troubleshooting guide for more details
2. Connect the cable and read the registers again
   1. I imagine in your case it will link up because you mentioned that register access 'fixes' the link problem
3. If my comment on step 2.a is correct, please power off the board, connect the cable, and power on again, then read registers 0x0-1F
   1. The goal is to compare the registers in a working and non-working case.

Regards,

Alvaro

Hi Alvaro,

Please find the register details in the attached Excel sheet for the scenario you have suggested. 

Kindly let me know if you need any other information.

ETH_REG.xlsx

Regards,

Gireesh

Hi Gireesh,

Thank you for providing the register reads so clearly. The registers that changed values are expected, nothing strange. Please allow me another day to review with my team about further debug steps.

Regards,

Alvaro

Hi Gireesh,

In your testing, how are you detecting link? Is it by checking an LED, terminal status, or register read?

Regards,

Alvaro

Hi Alvaro,

We have been monitoring the debug log of the processor (MAC) to verify the link-up status.

However, the link-up message does not appear on the issue boards.

Regards,

Gireesh

Hi Gireesh,

I understand the issue more now, to confirm:

On a working board: 

PHY links up and terminal log message notifies of link up (as pictured in your most recent reply).

On issue board:

This link up message never appears, however if you were to read any register (Read register 0x01 for example), this would cause the terminal log message to appear?

Could you read registers 0x6E & 0x6F again on a working board? In your ETH_REG file, Reg 0x6E= 0000, which is strange, I expected Reg 0x6E = 0800 (SGMII enable).

Regards,

Alvaro

Hi Alvaro,

We have once again read the 0x6E register and observed that the value is 0000 and, the value for the 0x6F register is 3000.

Alvaro: "This link-up message never appears, however, if you were to read any register (Read register 0x01 for example), this would cause the terminal log message to appear?

Gireesh Response: The sequence of MDIO access matters. If we access the MDIO first and then check the link status, the link-up message appears. However, if we check the link status first and then access the MDIO, we will get the link-up message only on the next power cycle.

All your understanding of the issue is correct, in addition to that I want to report an unusual observation we have encountered with the PHY. We have noticed that once we access the PHY through MDIO, the link successfully establishes for multiple subsequent power cycles without requiring additional MDIO access. However, after an indeterminate number of power cycles, the link fails again. At this point, it necessitates another MDIO access to successfully establish the link.

This intermittent issue does not seem to follow a fixed pattern and appears to occur randomly after varying numbers of power cycles.

I have attached a diagram to explain the above observation. If it is not clear, we shall have a call to discuss it further.

Link up issue-Phy behaviour.pptx

Regards,

Gireesh 

Hi Gireesh,

Please let's set up a call, could you reach out to your local FAE to contact me via email?

Regards,

Alvaro