TCAN4550-Q1: Crystal configuration

Hi Daniel,

Yes, the bit rate must be an integer multiple of the Crystal frequency.

CAN and CAN FD bit timing requires an integer number of clock cycles (called time quantum or "tq" for short) to allocated for a single bit.  Allocating more or less tq will increase or decrease the bit width, which in turn determines the bit rate.  Therefore 32MHz clock cycles or tq would be used to create a 2Mbps data bit with 16 clock cycles or tq for a 2Mbps data bit.  However, 5Mbps is not an integer multiple of 32MHz, so it would not be possible.

As long as there is an integer number of clock cycles for the bit rate, and the clock is at least 5x the bit rate (because there is a minimum of 5tq per CAN bit), the bit width should be achievable.

While it is not recommended to use a clock frequency less than 20MHz, it may be possible to communicate but you should note that other timing parameters in the TCAN4550 will also be affected by this slower clock such as the watchdog timer, the Sleep Wake Error (SWE) Failsafe timer, etc.  If a clock frequency other than 20MHz or 40MHz is used, then the 20MHz or 40MHz frequency closest to the actual clock frequency used should be selected in the CLK_REF  in the Modes of Operation and Pin Configuration Register (0x0800[27]).  Then the timer values will need to be scaled according to the difference between the actual clock frequency and the selected 20MHz or 40MHz clock selected.

Industry standard clock frequencies for CAN are 20MHz, 40MHz, and 80MHz and it is recommended that all devices on a CAN bus have the same bit timing configuration settings and an equivalent number of time quantum. Bit sampling errors can occur when nodes have different settings.  Using an 8MHz clock may be possible but it also may result in some communication errors and should be thoroughly tested.

Regards,

Jonathan