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DP83822I: VDDIO and VAVD ramp sequence

Dean Hofstetter
Expert 2565 points
Part Number: DP83822I

Tool/software:

Figure 7-1 from the datasheet shows VDDIO becoming stable before VAVD begins to rise.  The T1 number from the 7.6 Table, says that it can be +/- 100mS.  Which means that VAVD could power up before VDDIO, or they can power up at the same time.  However note number three states:  "AVD ramping up AFTER VDDIO ramp completion is preferred to avoid false detection of lower level VDDIO in any corner case".  What exactly does that mean?

I've checked the DP83822 Schematic Checklist and there is no mention of making sure VAVD ramps after VDDIO.  I've checked the EVM schematic, and VAVD and VDDIO ramp at the same time.  Basically outside of this note #3 from Table 7.6, and can see no effort on TI's part to follow this guidance.  Therefore, is it required?  Helpful?  Not needed?  Other?  Please explain.

Thanks, Dean

  • +1
    TI__Genius 13872 points

    Hi Dean,

    This guidance is recommended, however the false detection corner case is not expected to occur with AVD and VDDIO configured to ramp at the same time.

    The false detection occurs when AVD finishes ramping and samples the VDDIO voltage while this rail is still ramping. In this case, the PHY can incorrectly read the VDDIO voltage before the rail finishes ramping.

    Thank you,

    Evan

  • 0 in reply to Evan Mayhew
    Expert 2565 points

    If that is the case, then T1 from Table 7.6 should be:  MIN = 0mS, MAX=100mS   ..and..   note #3 could simply say that AVD should not exceed VDDIO during ramp.  It would then be clear that AVD should never ramp before VDDIO, and that having both rails ramp at the same time is acceptable.  At any rate, you've answered my question.

    Thanks, Dean