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TCAN4550-Q1: the allocation of 2Kb RAM space

Grey Guo
Prodigy 450 points
Part Number: TCAN4550-Q1
Other Parts Discussed in Thread: TCAN4550

Tool/software:

Hi team,

My customer has two questions about TCAN4550:

1. Does TCAN4550's communication support trigger interrupt? If it does, what configuration is needed to do for TCAN4550?

2. How does TCAN4550 allocate the 2K RAM space shared by RX and TX (How many RX, how many TX) ? Is there a calculation formula? And since the data length of CAN and CAN FD are different, do CAN and CANFD occupy different data area?

Pls kindly give some help. Thanks!

Best,

Grey

  • 0
    TI__Mastermind 24840 points

    Hi Grey,

    Grey Guo said:
    1. Does TCAN4550's communication support trigger interrupt? If it does, what configuration is needed to do for TCAN4550?

    Please explain what you mean by "trigger interrupt".

    Grey Guo said:
    2. How does TCAN4550 allocate the 2K RAM space shared by RX and TX (How many RX, how many TX) ? Is there a calculation formula? And since the data length of CAN and CAN FD are different, do CAN and CANFD occupy different data area?

    Please see the TCAN455xx Software User's Guide (Link) and the MCAN User's Manual (Link) for information on how to configure the MRAM for the various elements needed in the application.

    Each application is unique and may require different amount of RX and TX Buffers, SID and XID filters, and therefore the 2K of MRAM can be allocated to based on the customer's preference.  MCAN does not require any type of element to be used, or for any minimum number of element in any type. 

    There is only 2K of MRAM occupying address 0x8000 to 0x87FF for all of the different memory elements.  It is not possible to allocate the maximum number of elements supported by MCAN, so you will need to determine what your application needs and ensure it fits within the MRAM without overlapping addresses. 

    If your configuration exceeds 2K, the memory cycles back to the beginning of the address space.  For example, if you attempt to read or write from address 0x8800, this is the same as a read or write to 0x8000.

    The TX Buffer size will need to be set large enough to hold the longest CAN or CAN FD message you intend to transmit.  Therefore, if you intend to transmit a CAN FD message with 64 data bytes, then all of your TX Buffers will need to be able to store 64 data bytes.  The message header indicates how many data bytes are being transmitted, so any message that has fewer data bytes than the TX Buffer will hold (i.e. 8 bytes) will only transmit the number of data bytes indicated in the message header.

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    TI__Prodigy 450 points

    Hi Jonathan,

    Thanks for your reply and detailed explanation! The customer's method of receiving CAN messages is to read the SPI Rx buffer in turn in the periodic tasks. But if the task is blocked, CAN messages may not be able to read in time, causing the buffer to be full and causing frame loss.

    They want to reduce the risk of frame loss by 2 ways: (1) Enlarge the Rx buffer. (2) Improve the reading efficiency through interrupts.

    So they want to know under what conditions can the TCAN4550 generate an output on the interrupt pin.

    Thanks.

    Best,

    Grey

  • 0 in reply to Grey Guo
    TI__Mastermind 24840 points

    Hi Grey,

    There are several RX FIFO related interrupt bits in the MCAN Interrupt register 0x1050 that can be enabled in register 0x1054.  You will also need to enable the MCAN Interrupt Line (usually Line 0 - EINT0) in the Interrupt Line Enable register 0x105C.

    You can generate an interrupt for every message, or you can assign a "watermark level" to interrupt on after a particular number of messages have arrived which should allow the processor time to read and clear the FIFO before it becomes full and overflows.

    Regards,

    Jonathan