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DP83867E: VDDIO voltage level

Buddika Sumanasena
Prodigy 40 points
Part Number: DP83867E

Tool/software:

I am bit confused about the VDDIO of DP83867E. Section 6.3 Recommended Operating Conditions says three options for VDDIO namely 3.3V option, 2.5V option and 1.8V option. Does it mean one of these options has to be selected when ordering the part? Or we can just supply any voltage out of 3.3V, 2.5V and 1.8V and design accordingly.

  • +1
    TI__Mastermind 31005 points

    Hello,

    The VDDIO is independent of the part ordering. When you use our part, you may use it in multiple different VDDIO configurations as required by your system.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 40 points

    I have one more question. In the design checklist SLVRBN1A.xlxs spreadsheet it is recommended to use a BJT to drive LEDs if 1.8V is used.

    According to the Figure 7-12. LED Operation From 1.8V I/O VDD Supply given in both datasheet and the spreadsheet the voltage at the pin LED_2 is cannot be higher than Vbe of the transistor. So regardless of the resistor values we probably cant set the strap value of LED_2 to Mode 4 for example.

    So, why not use a MOSFET and avoid this issue? Also if a MOSFET is used does the gate capacitance of the MOSFET affect the initial value read by the strap pin. This is because it might take some time for the gate capacitance to charge to to value set by the resistor devider. If the voltage is read before the gate capacitance gets charged we might read a lower value. Any thoughts on this?

    Thank you very much for the reply.

  • +1 in reply to Buddika Sumanasena
    TI__Mastermind 31005 points

    Hello,

    For strapping, the resistor network is utilized while pin is treated as HI-Z. At this point, the strap is sampled with the BJT base acts as an open for all intents and purposes. Upon active operation, the PHY will be driving the pin between 0V and VDDIO so the transistor will turn-on.

    You are also free to use a MOSFET configuration, and we do not expect the gate capacitance to affect the initial read value as this capacitance is relatively small.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 40 points

    I have one question regarding strapping pin details given in design checklist SLVRBN1A.xlxs spreadsheet. It has strap pins RX_D0 to RX_D7. But the chip only has RX_D0 to RX_D3 (pins 33,34,35 and 36). Why is this?

    Hardware Configuration Feature Select Default Value Strap Pin Strap Mode Recommend Pull up (RH) Recommend Pull Down (RL)
    PHY Address 10 0 RX_D0 3 5.76kΩ 2.49kΩ
    RX_D2 3 5.76kΩ 2.49kΩ
    RX_D4 1 Open Open
    MDI/X (Don't Care if Auto-MDIX enabled)
    Duplex (Don't Care if Auto-Negotiation enabled)    		 MDI
    Full Duplex    		 MDI
    Full Duplex    		 RX_D5 1 Open Open
    Auto-MDIX
    MAC Interface    		 Enabled
    RGMII    		 Enabled
    RGMII    		 RX_D6 1 Open Open
    Speed Optimization (0x14[9])
    CLK OUT (0x170[6])    		 Disabled
    Enabled    		 Disabled
    Enabled    		 RX_D7 1 Open Open
    Auto-Negotiation Enabled RESERVED
    Must strap to mode 3 or 4    		 RX_CTRL/RX_DV 3 5.76kΩ 2.49kΩ
    Fast Link Drop Disabled Disabled CRS 1 Open Open
    Auto-Negotiation Advertisements
    (Don't Care if Auto-Negotiation is disabled)    		 10/100/1000 10/100/1000 LED_1 1 Open Open
    Port Mirroring Enabled Disabled LED_0 3 5.76kΩ 2.49kΩ
  • 0 in reply to Buddika Sumanasena
    TI__Mastermind 31005 points

    Hello, 

    Have you checked which strap section is being used?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 40 points

    Hi,

    I was looking at the wrong sheet.

    Thank you very much for the help.

    Best regards,

    Buddika