DP83867IS: SGMII not communicating and INT_TST_MODE_1 set to 1

Hi Emanuele,

Thank you for submitting your query, I'll be glad to help you.

Emanuele Ghidoli said:

CFG4 value: 0x1090 - INT_TST_MODE_1 is 1

This is not expected and likely to be the issue. Please read both Registers 0x6E & 0x6F to confirm if the PHY is being strapped as expected. For example you're expecting RX_CTRL to be in mode 3 but it is getting configured differently. Please see this FAQ for more information.

Regards,

Alvaro

Hello Alvaro,

reg 0x006E STRAP_STS1 value 0x0804

reg 0x006F STRAP_STS2 value 0x0100

The "1" in STRAP_STS2 is the bit reported in INT_TST_MODE_1 register description.

We have double checked RX_CTRL and the voltage during reset is for mode 3 (0.44 V over VDDIO 1.8 V).

RX_CTRL is not connected except for the resistors selecting the mode.

Is there any other strap option that can affect the bit in STRAP_STS2?

Thanks.

Kind regards,

Emanuele

I would like to share that we are also investigating on the SoC side https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1385122/dp83867is-sgmii-not-communicating-and-int_tst_mode_1-set-to-1 .

Currently I'm inclined to think that the problem is on phy side. At least here we have something not "consistent".

I would like to share the related schematic page

SGMII ethernet schematic

Hi Emanuele,

The schematic strap resistors for RX_CTRL look good, please allow me another day to check an SGMII board in lab.

Regards,

Alvaro

In seems like the Linux kernel is coping with this "problem". The comment is about link instability.

https://elixir.bootlin.com/linux/v6.10-rc7/source/drivers/net/phy/dp83867.c#L914

Introduced: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=371444764b9882d754d1e67dd212c932359a2293

Extended to SGMII phy (they set bit 8 of CFG4... I think it is an error. It is reserved! ):

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0c9efbd5c50c64ead434960a404c9c9a097b0403

Activating the quirk leads to:

Reg 0x006E: 0x0804

Reg 0x006F: 0x0100

Reg 0x0031: 0x1110

But, in every case, SGMII link with AM69 SoC still does not work.

Hi Alvaro,

About Loopback Mode how can I activate the MII loopback?

Am I right that it loopback the signal coming from SoC SGMII TX to SoC SGMII RX?

Is it of value to debug the SGMII link?

Have you other suggestions?

Best regards,

Emanuele

Hi Emanuele,

In lab I used two DP83867ERGZ-S-EVMs (the SGMII capable EVM) in the following configuration.

Smart Bits (Data Generator) <-Ethernet Cable-> x867-S-EVM <-SGMII-> x867-S-EVM <-Ethernet Cable-> Smart Bits (Data Generator)

Communication was tested at 1Gbps and Smart bits is able to confirm Packets Transmitted = Packets Received, with 0 errors. With this stable set up, I read the following registers:

• Reg 0x6E = 0x8820
  • SGMII Enabled, auto-neg enabled
• Reg 0x6F = 0x0110
  • Bit [8] is high
• Reg 0x31 = 0x10B1 -or- 0x2163
  • This value would change every few register reads
  • I read this register during 1Gbps communication. Please confirm if this register value is inconsistent for you as well. 
• Reg 0x37 = 0x0001 -or- 0x0003 (read this register several times, bit[0] should consistently be high during stable SGMII link)
  • When SGMII link is disconnected, bit[0] sometimes read high, read several times to confirm

To configure the x867 in MII Loopback, please follow the following Register writes:

• Reg 0xFE = 0xE720
• Reg 0x00 = 0x4140
  • MII Loopback Enabled, auto-neg disabled, and Speed select 1000Mbps (bits 13 & 6)

Please let me know if this helps configure your x867.

Regards

Alvaro

Hello Alvaro,
my registers:
- Reg 0x6E = 0x0804 (you have port mirroring and ANEG_SEL which configures 100/1000 instead of 10/100/100
- Reg 0x6F = 0x0100 (you have a difference on STRAP_RGMII_CLK_SKEW_TX, which should be not relevant)
- Reg 0x31 = 0x1110 ( I think you reported the wrong register, this register does not change normally. It is CFG4, configuration register)
- Reg 0x37 = 0x0000 (This one is saying to me "nothing working on SGMII...")

I have configured MII loopback hoping to obtain a link status good on SoC but... nothing.

For sure having a register set to compare with, helps a lot.

Thank you.

Regards,

Emanuele

Hi Emanuele,

Thank you for confirming your Registers. Reg 0x37 = 0 and MII loopback not working definitely hints towards the issue being with the SGMII connection. To confirm, are you able to get link on the connector side (read Reg 0x1)? Could you also check if SGMII_AUTONEG is enabled (Reg 0x14[7])? 

Are we sure that the SoC is configured correctly for SGMII?

Regards,

Alvaro

Hi Alvaro,
- Reg 0x01: 0x796d (link status 1, confirmed also by the counterpart)
- Reg 0x14: 0x2bc7 (SGMII_AUTONEG_EN 1)

> Are we sure that the SoC is configured correctly for SGMII?
No... I'm not sure. In theory, all the registers are "correct": https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1385154/am69-sgmii-not-working-with-dp83867is

Kind regards,
Emanuele

Hi Emanuele, 

I would confirm if it is configured correctly first. If you have an oscilloscope, you can try probing the SGMII lines and see if the PHY and SoC are both transmitting or not.

Regards,

Alvaro

Hi Alvaro,
we have done some acquisitions both on N Tx and Rx side. It seems they are transmitting.

Kind regards,

Emanuele