Other Parts Discussed in Thread: DP83867IS
Tool/software:
Hello,
We are using kernel ti-linux-6.1.y, SDK version 09.02.00.010 and we applied a patch proposed on this forum question: e2e.ti.com/.../
We are trying to communicate over SGMII with TI DP83867IS, without any success.
We are able to communicate through MDIO with the PHY and we are able to read and write PHY registers from linux (using phytool).
We see the relevant sw interface (eth1), link up/down are detected, but packet trasmitted are not sent over the ethernet and we are not able to receive any packet.
Communication with the phy, on ethernet, is working because if we activate reverse loopback mode on the phy we are able to loop back packets coming from my notebook (link at 1 Gb).
About SGMII we know that PHY reports SGMII_ANEG_STS 0x0000 which means no SGMII page receive / SGMII Auto-Neg not complete.
I read out the values of some registers on the main_cpsw0:
0x0C000100: 0x4EC21102 0x0C000200: 0x4EC21102 0x0C000204: 0x00000000 0x0C000210: 0x00000001 0x0C000214: 0x00000030 0x0C000218: 0x00000001 0x0C00021C: 0x00000000 0x0C000220: 0x00004000 0x0C000224: 0x00000000 0x0C000240: 0x00000000 0x0C000244: 0x00000000 0x0C000248: 0x00000F91 0x0C03A000: 0x000001BF 0x0C03A004: 0x00000178 0x0C03A008: 0x00000047 0x0C03A00C: 0x00000000 0x0C03A010: 0x00000000 0x0C03A014: 0x00000000 0x0C03A018: 0x00000000 0x0C03A01C: 0x00000000 0x0C03A020: 0x00000000 0x0C03A024: 0x00000000 0x0C03A028: 0x00000000 0x0C03A02C: 0x00000000 0x0C03A030: 0x0002FF1A 0x0C03A034: 0x00000000 0x0C03A038: 0x00000000 0x0C03A03C: 0x00000000 0x0C03A040: 0x00000000 0x0C03A044: 0x00000000 0x0C03A048: 0x00000000 0x0C03A04C: 0x00000000 0x0C03A050: 0x00000000 0x0C03A054: 0x00000000 0x0C03A058: 0x00000000 0x0C03A05C: 0x00000000 0x0C03A060: 0x00000000 0x0C03A064: 0x00000000 0x0C03A400: 0x00000000 0x0C03A434: 0x00000000 0x0C03A234: 0x00000000 0x0C03A634: 0x00000000 0x0C03A404: 0x00000000 0x0C03A408: 0x00000000 0x0C03A40C: 0x00000000 0x0C03A410: 0x00000000 0x0C03A414: 0x00000000 0x0C03A418: 0x00000000 0x0C03A41C: 0x00000000 0x0C03A420: 0x00000000 0x0C03A424: 0x00000000 0x0C03A428: 0x00000000 0x0C03A42C: 0x00000000 0x0C03A430: 0x00000000 0x0C03A434: 0x00000000 0x0C03A438: 0x00000000 0x0C03A43C: 0x00000000 0x0C03A440: 0x00000000
This is an excerpt of the device tree:
/ {
aliases {
ethernet0 = &mcu_cpsw_port1; /* Not relevant -- it is working! */
ethernet1 = &main_cpsw0_port2;
};
mdio_eth2: mdio {
compatible = "virtual,mdio-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_main_mdio0>;
#address-cells = <1>;
#size-cells = <0>;
gpios = <&main_gpio0 48 GPIO_ACTIVE_HIGH>, /* MDC */
<&main_gpio0 47 GPIO_ACTIVE_HIGH>; /* MDIO */
cpsw0_port2_phy4: ethernet-phy@4 {
reg = <4>;
device_type = "ethernet-phy";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth2_int>;
interrupt-parent = <&main_gpio0>;
interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
};
};
};
&main_pmx0 {
pinctrl_eth2_int: main-gpio0-44-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 7) /* (AL33) MCASP1_AXR3.GPIO0_44 */ /* AQUILA B81 */
>;
};
};
&serdes1 {
status = "okay";
serdes1_pcie0_2l_link: phy@0 {
reg = <0>;
#phy-cells = <0>;
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
cdns,num-lanes = <2>;
cdns,phy-type = <PHY_TYPE_PCIE>;
};
serdes1_pcie2_1l_link: phy@2 {
reg = <2>;
#phy-cells = <0>;
resets = <&serdes_wiz1 3>;
cdns,num-lanes = <1>;
cdns,phy-type = <PHY_TYPE_PCIE>;
};
serdes1_sgmii_link: phy@3 {
reg = <3>;
#phy-cells = <0>;
resets = <&serdes_wiz1 4>;
cdns,num-lanes = <1>;
cdns,phy-type = <PHY_TYPE_SGMII>;
};
};
&serdes_refclk {
clock-frequency = <100000000>;
};
&serdes_ln_ctrl {
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, /* Aquila PCIE_2 L0 */
<J784S4_SERDES0_LANE1_PCIE1_LANE1>, /* Aquila PCIE_2 L1 */
<J784S4_SERDES0_LANE2_PCIE3_LANE0>, /* On-module PCIe Wi-Fi */
<J784S4_SERDES0_LANE3_USB>, /* Aquila USB0 SS */
<J784S4_SERDES1_LANE0_PCIE0_LANE0>, /* Aquila PCIE_1 L0 */
<J784S4_SERDES1_LANE1_PCIE0_LANE1>, /* Aquila PCIE_1 L1 */
<J784S4_SERDES1_LANE2_PCIE2_LANE0>, /* On-module PCIe USB Bridge */
<J784S4_SERDES1_LANE3_QSGMII_LANE2>, /* Aquila ETH_2 xGMII */
<J784S4_SERDES2_LANE0_IP4_UNUSED>, /* Aquila SGMII MSP_6 */
<J784S4_SERDES2_LANE1_IP4_UNUSED>, /* Aquila SGMII MSP_7 */
<J784S4_SERDES2_LANE2_IP4_UNUSED>, /* Aquila SGMII MSP_8 */
<J784S4_SERDES2_LANE3_IP4_UNUSED>, /* Aquila SGMII MSP_9 */
<J784S4_SERDES4_LANE0_EDP_LANE0>, /* Aquila DP L0 */
<J784S4_SERDES4_LANE1_EDP_LANE1>, /* Aquila DP L1 */
<J784S4_SERDES4_LANE2_EDP_LANE2>, /* Aquila DP L2 */
<J784S4_SERDES4_LANE3_EDP_LANE3>; /* Aquila DP L3 */
};
&serdes_wiz1 {
status = "okay";
};
&main_cpsw0_port2 {
phy-mode = "sgmii";
phys = <&cpsw0_phy_gmii_sel 2>, <&serdes1_sgmii_link>;
phy-names = "mac", "serdes";
phy-handle = <&cpsw0_port2_phy4>;
status = "okay";
};
&main_cpsw0 {
status = "okay";
};
Any idea?
Best regards,
Emanuele
