AM69: SGMII support for a single DP83867 PHY from SERDES

Hello,

Our expert is out of office on holiday. Please expect a response at the beginning of next week.

Thanks,

Erick

Hi Tanmay,

Thank you for a quick response. Just to re-confirm, If we patch AM69 CPSW driver as per below [1] (suggested by you), and add proper 'phy-mode' property as below [2], we should be good to use SERDES single lane for SGMII phy configuration.

Correct ? Or is there any other place too which needs modification for SGMII support from SERDES single lane ?

[1]

diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index 684c6e120e1c..69868235f2cf 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -2899,7 +2899,8 @@ static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = {
        .quirks = 0,
        .ale_dev_id = "am64-cpswxg",
        .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
-       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII),
+       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
+                         BIT(PHY_INTERFACE_MODE_USXGMII),
 };
 
 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 2828f888ad92..d328a1c65264 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -249,7 +249,8 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
        .use_of_data = true,
        .regfields = phy_gmii_sel_fields_am654,
        .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
-                      BIT(PHY_INTERFACE_MODE_USXGMII),
+                      BIT(PHY_INTERFACE_MODE_SGMII) |
+                      BIT(PHY_INTERFACE_MODE_USXGMII),
        .num_ports = 8,
        .num_qsgmii_main_ports = 2,
 };

[2]

&main_cpsw0_port5 {
    phy-handle = <&cpsw9g_phy0>;
    phy-mode = "sgmii";
    phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
    phy-names = "mac", "serdes";
    status = "okay";
};

One more followup question,

will u-boot also supports such SGMII configuration ( with above changes) for SERDES ? We plan to use the mentioned ethernet port as a main interface which must be supported in u-boot too.

Appreciate your support. Thank you.

Regards,

Parth P

Hi Parth,

Parth Pancholi said:

Correct ? Or is there any other place too which needs modification for SGMII support from SERDES single lane ?

You would have to modify the serdes node for sgmii link as well, the "serdes2_qsgmii_link" node. Depending upon the lane used, you have to modify the node and put "cdns,phy-type" as "PHY_TYPE_SGMII". As well as configure the "serdes_ln_ctrl" for a lane from cpsw MAC.

Refer to this documentation for more details.

Parth Pancholi said:

will u-boot also supports such SGMII configuration ( with above changes) for SERDES ? We plan to use the mentioned ethernet port as a main interface which must be supported in u-boot too.

Theoretically the u-boot can support SGMII configuration, but currently driver level support is not present in u-boot to get SGMII link in u-boot. These changes will not be sufficient for u-boot. 

Regards,
Tanmay

Hi Tanmay,

Thank you for response. I have some doubts on below comment for enabling the SGMII.

Tanmay Patil said:

You would have to modify the serdes node for sgmii link as well, the "serdes2_qsgmii_link" node. Depending upon the lane used, you have to modify the node and put "cdns,phy-type" as "PHY_TYPE_SGMII". As well as configure the "serdes_ln_ctrl" for a lane from cpsw MAC.

main_cpsw0_port5 {
    phy-handle = <&cpsw9g_phy0>;
    phy-mode = "sgmii";
    phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
    phy-names = "mac", "serdes";
    status = "okay";
};

&serdes2 {
	status = "okay";

	serdes2_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		#phy-cells = <0>;
		resets = <&serdes_wiz2 1>;
	};
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
			  <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>,
			  <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
			  <J784S4_SERDES1_LANE2_PCIE2_LANE0>, <J784S4_SERDES2_LANE0_QSGMII_LANE5>,
			  <J784S4_SERDES4_LANE0_EDP_LANE0>, <J784S4_SERDES4_LANE1_EDP_LANE1>,
			  <J784S4_SERDES4_LANE2_EDP_LANE2>, <J784S4_SERDES4_LANE3_EDP_LANE3>;
};

From the documentation link, I could configure SERDES2 -> LANE0 -> SGMII5 as mentioned in above DT snippest. However, I have doubts on 'serdes_ln_ctrl' property as I could not see any specific MUX for SERDES SGMII mode on bindings 'include/dt-bindings/mux/ti-serdes.h' file for J784S4.

What should be the value for specific SERDES LANE config under serdes_ln_ctrl for SGMII support on AM69 ? If we use 'J784S4_SERDES2_LANE0_QSGMII_LANE5' that should not be right as per my understanding. Please correct me if I am wrong.

In addition, please correct me if something is still missing/incorrect in above DT snippet to enable SGMII from SERDES2 on AM69.

Thank you.

Regards,

Parth P