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DP83867IS: DP83867ISRGZ related issues

jeno.zhang
Expert 2315 points
Part Number: DP83867IS

Tool/software:

Hi，

Question 1: DP83867ISRGZ uses RGMII for connection, what is the rise and fall time of the output RX-CLK signal?

Question 2: Find a parameter in the manual as shown in the following figure, but it is not specified whether it is an input parameter for TXCLK or an output parameter for RXCLK.

Question 3: 

The MAC used by the customer requires an input clock rise and fall time of 0.54ns. Is there any way to adjust the rise and fall time of the DP83867 output clock signal?

Thanks!

  • 0
    TI__Genius 17486 points

    Hi Jeno,

    Question 1 & 2

    You got it, this is the RGMII spec for the RX_CLK. I understand the confusion but this would apply to both RGMII clocks.

    Question 3:

    Why does the MAC need such a quick rise time? We can make the rise time quicker by writing to Register 0x170[4:0]. Setting bits 4:0 = '11111' will make the MAC output impedance the lowest, hence making the rise time the quickest. However I am unsure if it can meet the 0.54ns requirement. 

    Regards,

    Alvaro