DP83TG720S-Q1: How to configure DP83TG720S-Q1to boot up in RGMII mode

Laurence Cook

Part Number: DP83TG720S-Q1

Tool/software:

We don't understand which of these 4 strapping options are required so the chip boots up in RGMII mode - See datasheet Table 7-19.

Do we use Align mode, TX shift mode, or what? Clearly it is one of the lower 4 options but which one? Please explain! In our design the PHY is connected to an Auto-Ethernet switch which only has an RGMII port available.

8 months ago

0 Avtar Dhaliwal 8 months ago

TI__Expert 4740 points

Hi Laurence,

Here is a helpful FAQ on picking as well as implementing RGMII shift or align mode to meet your design needs:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1096129/faq-rgmii-timing---align-and-shift-mode

Regards,

Avtar

0 Laurence Cook 8 months ago in reply to Avtar Dhaliwal

Prodigy 100 points

Thank you Avtar, I am sorry for the delay in replying! The auto-ethernet switch that's connected to the TI PHY can be programmed to add internal 2ns clock delay on TX and TX, so we think the PHY should be configured for align mode in hardware. However I now have a related question. Clearly we need to match the 4 data lines and associated clock line to a very tight tolerance (1ns or less?) but does the same critical requirement also apply to the RX_CTRL, TX_CTRL line track lengths with respect to clocks? In other words we have to have all 6 tracks closely length matched?

+1 Avtar Dhaliwal 8 months ago in reply to Laurence Cook

TI__Expert 4740 points

Hi Laurence,

Yes all data lines and RX_CTRL / TX_CTRL need to be closely length matched.

Regards,

Avtar

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DP83TG720S-Q1: How to configure DP83TG720S-Q1to boot up in RGMII mode