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TL16CP754CIPM Register Description

Other Parts Discussed in Thread: TL16C754C

Hi,

We are using TL16CP754CIPM from Texas Instruments.

We have some observations which are different from as described in UART controller datasheet.

  1. We want to have a Modem Interrupt. To enable this IER[3] is set to 1. I can see that INTA ping being toggled. But, when we read on this pin going high IIR shows a value of 0x1, which means there is no interrupt.
  2. Can you please clarify what is the value for IIR[5:0] when modem interrupt is generated. In TI's data sheet it shows a value of 0x8 but when we see the exar datasheet part number (ST16C654) it shows a value of 0x0. Please clarify this
  3. MSR[4] shows a value of zero when /CTS is low and a value of 1 when /CTS is High
  4. Similarly to make /RTS low we have to write a value of 0 and a value of 1 to make it high which contradicts with the description given against it.

Please help us in understading it.

Regards,

GSR

  • Hi All,

    For example the MCR register describes that if we wwrite MCR[1] = 0 Forces /RTS to inactive or a logical state equals to High.

    But our observation is after writing MCR[1] = 1 /RTS signal goes high.

    Similarly ot make RTS low we have to write MCR[1] = 0.

    Is this expected or else we are doing some thing wrong. Please help us in understanding this

    Regards,

    GSR

  • Hello GSR,

    I will look at this on the bench and verify the functionality. I will get a response to you later today.

    Best Regards,

    Joe

  • Hi  GSR,

    Attached are two scope captures from a Tek MSO4104 scope. One is /RTS and /DTS when writing a 0x07 to the MCR register (BASE +  04) and the other shows /RST and /DTS when writing a 0x00 to the MCR. /RTS and /DTS are labeled in the captures. Bus B1 is the data bus and Bus B2 is the address bus.

    Please let me know if you have any questions.

    For some reason I can only attache one picture to this message. I'll post the capture then send another reply with the second capture.

    Thank you.

    Best Regards,

    Joe

  • GSR,

    here is the other capture, writing 0x00 to the MCR

  • Hi Joe Fockler.

    Thank You so much for your time.

    Sorry, I didn't notice that there is a Transceiver between TL16C754C and the connector which connects to the PC.

    When we probe at TL16C754C now we do observe the same what you are observing.

    Regards,

    GSR

  • Hi GSR,

    Is the interrupt issue resolved?

    Best Regards,

    Joe

  • Hi Joe,

    I haven't tested yet. I will let you know the results after testing.

    Regards,

    GSR

  • Hi Joe,

    We are facing one issue w.r.t. Tx. When we transmit we are observing some junk junk characters.

    I have printed the data in the buffer that is passed by Application to Driver and observed that data is correct.

    For example when we transferred 192 bytes data, the following data is observed on Tera Term with following settings 115200-Baud, 8-Data Bits, No Parity, 1=Stop Bit and no Flow control

    W

       ?ÍѹL]???Íѹ?]???Íѹ?]???Íѹ?]???ÍѹÕÿ Write test. F 6 Write test. F 7 Write test. F 8 Write test. F 9 Write test. F 0 Write test. F 1 Write test. F 0 Write test. F 1 Write test. F 2 Write test. F 3 Write test. F 4 Write test. F 5 Write test

    We are writing to THR register in CPU mode. The code for it pasted below

     

    while(u32BytesToSent)

    {

     

    do

    {

    u8LSR = pPDD->pstrUARTReg->cu8LSR;

     

    if((u8LSR & 0x20) == 0x20)

     

    break;

    }

    while(1);

     

    //while((u8LSR & UART_LSR_THR_EMPTY) == FALSE);

    pPDD->pstrUARTReg->u8THR = *pu8SrcBuff++;

    (*pu32NoOfBytes)++;

    u32BytesToSent--;

    }

    Thanks for your time.

    Additional observation is we never faced this issue when the baud rate is 9600. But for 115200, we see this problem very often. The crystal input to controller 1.8432MHz. Please let us know if there is any errata on this.

    Regards,

    GSR

  • Hi All,

    Thanks for your time. We are able to identify the problem. RS-232 Transceiver is the culprit.

    Regards,

    GSR