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SN65DSI86-Q1: Problem with DSI to DP monitor output

kisung park
Prodigy 10 points
Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: TEST2, SN65DSI86

Tool/software:

I designed a DSI to DP board using SN65DSI86-Q1 to output FHD camera images to DP monitor.

However, the DSI output is confirmed on the soc, but only a black screen is displayed on the DP monitor.

I output a color bar from SN65DSI86-Q1 and confirmed it on the DP monitor.


1. Circuit diagram

DSItoDP_Rev0.1_20240726.pdf
2. init data

// ======Soft reset ======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x09, 0x01, 1, 1);
ERR_CHECK_RET(ret,-1);
// ======REFCLK 27MHz ======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x0A, 0x04, 1, 1); // 26
ERR_CHECK_RET(ret,-1);

//======ASSR RW control ======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0xFF, 0x07, 1, 1);
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x16, 0x01, 1, 1);
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0xFF, 0x00, 1, 1);

//======Single 4 DSI lanes======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x10, 0x26, 1, 1); // channel A,B 4lane set
ERR_CHECK_RET(ret,-1);

//======DSIA CLK FREQ 445MHz======
// Set automatically after EN setting
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x12, 0x56, 1, 1);
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x12, 0x59, 1, 1); // 445Mhz
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x12, 0x60, 1, 1);// 480Mhz
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x12, 0x65, 1, 1);// 480Mhz
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x12, 0xC0, 1, 1);// 750Mhz ( MAX 0x96 , 750Mhz)
ERR_CHECK_RET(ret,-1);
// ret = i2c_read_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x12, &read_data, 1,1); // r: 0x84
// printf("DSI65DSI86Q1_ADDR 0x12 = 0x%x\n", read_data);
//======DSIB CLK FREQ 445MHz======
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x13, 0x59, 1, 1);
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x13, 0x60, 1, 1);// 480Mhz ( MAX 0x96 , 750Mhz)
ERR_CHECK_RET(ret,-1);

//======enhanced framing and ASSR======

ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x5A, 0x04, 1, 1);

//======2 DP lanes no SSC======
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x93, 0x20, 1, 1);
//======1 DP lanes no SSC======
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x93, 0x10, 1, 1);
//======4 DP lanes no SSC======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x93, 0x30, 1, 1); // default
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x93, 0x70, 1, 1); // PRE 1
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x93, 0xB0, 1, 1);// PRE 2
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x93, 0xF0, 1, 1);// PRE 3
ERR_CHECK_RET(ret,-1);

//======HBR (2.7Gbps)======
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x94, 0xE0, 1, 1); // 5.4
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x94, 0x80, 1, 1); // 2.7
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x94, 0x20, 1, 1); // 1.62Gbps
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x94, 0x21, 1, 1); // SW 1
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x94, 0x22, 1, 1); // SW2
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x94, 0x23, 1, 1); // SW3
ERR_CHECK_RET(ret,-1);

//======PLL ENABLE======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x0D, 0x01, 1, 1);
ERR_CHECK_RET(ret,-1);
//======Verify PLL is locked======
// ret |= tixx_write_Only_reg(0x0A);

ret = i2c_read_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x0A, &read_data, 1,1); // r: 0x84
printf("DSI65DSI86Q1_ADDR 0x0A = 0x%x\n", read_data);


//======POST-Cursor2 0dB ======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x95, 0x00, 1, 1);
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x95, 0x40, 1, 1); // POST-Cursor2
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x95, 0x80, 1, 1);
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x95, 0xC0, 1, 1);
ERR_CHECK_RET(ret,-1);
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0xF8, 0xFF, 1, 1);

//======Semi-Auto TRAIN ======
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x01, 1, 1); //Normal mode (Idle pattern or active video)
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x02, 1, 1); // TPS1
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x03, 1, 1); // TPS2
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x04, 1, 1); // TPS3
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x05, 1, 1); // PRBS7
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x06, 1, 1); // HBR2
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x07, 1, 1); // 80-bit Custom Pattern
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x08, 1, 1); // Symbol Error Rate Measurement Pattern
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x09, 1, 1); // Fast Link Training
 ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x0A, 1, 1); // Semi-Auto Link Training.
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, 0x0B, 1, 1); // Redriver Semi-Auto Link Training

ERR_CHECK_RET(ret,-1);
sleep(0.02);

//Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 69
//Product Folder Links: SN65DSI86-Q1
//SN65DSI86-Q1
//SLLSEJ5A –JULY 2014–REVISED DECEMBER 2015 www.ti.com
//======Verify Training was successful======
// ret |= tixx_write_Only_reg(0x96);

ret = i2c_read_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x96, &read_data, 1,1);
printf("DSI65DSI86Q1_ADDR 0x96 = 0x%x\n", read_data);

ret = i2c_read_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x00, &read_data, 1,1);
printf("DSI65DSI86Q1_ADDR 0x96 = 0x%x\n", read_data);

//=====CHA_ACTIVE_LINE_LENGTH is 1920 =======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x20, 0x80, 1, 1);
ERR_CHECK_RET(ret,-1);
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x21, 0x07, 1, 1);
ERR_CHECK_RET(ret,-1);


//=====CHA_VERTICAL_DISPLAY_SIZE is 1080 =======

ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x24, 0x38, 1, 1);
ERR_CHECK_RET(ret,-1);
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x25, 0x04, 1, 1);
ERR_CHECK_RET(ret,-1);

//=====CHA_HSYNC_PULSE_WIDTH is 44 positive =======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x2C, 0x2C, 1, 1);
ERR_CHECK_RET(ret,-1);
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x2D, 0x00, 1, 1);
ERR_CHECK_RET(ret,-1);
//=====CHA_VSYNC_PULSE_WIDTH is 5 positive=======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x30, 0x05, 1, 1);
ERR_CHECK_RET(ret,-1);
// ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x31, 0x80, 1, 1); // default
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x31, 0x00, 1, 1);
ERR_CHECK_RET(ret,-1);


//=====CHA_HORIZONTAL_BACK_PORCH is 148=======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x34, 0x94, 1, 1);
ERR_CHECK_RET(ret,-1);
//=====CHA_VERTICAL_BACK_PORCH is 36=======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x36, 0x24, 1, 1);
ERR_CHECK_RET(ret,-1);
//=====CHA_HORIZONTAL_FRONT_PORCH is 88=======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x38, 0x58, 1, 1);
ERR_CHECK_RET(ret,-1);
//=====CHA_VERTICAL_FRONT_PORCH is 4=======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x3A, 0x04, 1, 1);
ERR_CHECK_RET(ret,-1);
//======DP- 24bpp======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x5B, 0x00, 1, 1);
ERR_CHECK_RET(ret,-1);

//======DP- 24bpp======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x5B, 0x00, 1, 1);
ERR_CHECK_RET(ret,-1);
//=====COLOR BAR disabled=======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x3C, 0x00, 1, 1);
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x3C, 0x10, 1, 1); // enable
//ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x3C, 0x12, 1, 1); // enable
ERR_CHECK_RET(ret,-1);

//======enhanced framing, ASSR, and Vstream enable======
ret = i2c_write_data_type(i2c_num, DSI65DSI86Q1_ADDR, 0x5A, 0x0C, 1, 1);
ERR_CHECK_RET(ret,-1);


3. Register status

  • 0
    Prodigy 10 points

    Hi

    In order to change to None ASSR, additional circuit modifications were made by referring to the contents below.

    This is a circuit diagram modified with a Pull UP on the Test2 pin to enable standard DP.

    DSItoDP_Rev0.2.pdf

    "DSI86 is designed with ASSR enabled by default to support the eDP panel. Most DP monitors or panels do not support ASSR. To support DP monitors, DSI86’s ASSR will need to be disabled by making ASSR_CONTROL read/write instead of read-only. The first step to make ASSR_CONTROL read/write is to make sure TEST2 pin is be sampled high at the rising edge of EN pin. It is recommended to pull TEST2 pin to 1.8V thru a 1k to 10k resistor. Once TEST2 is high, the following steps must be performed:

    1. Write 0x07 to register 0xFF. This will select Page 7.
    2. Write 0x01 to register 0x16. This will make ASSR_CONTROL to be read/write.
    3. Write 0x00 to register 0xFF. This will select Page 0.
    4. Write 0 to bits 1:0 at register 0x5A. This will change from ASSR to Standard DP."

    Thanks

    Parkks

  • 0 in reply to kisung park
    TI__Mastermind 38090 points

    Hi,

    Looks like error registers are set.

    0xF5 = 02

    0xF6 = 40

    0xF8 = 02

    Address 0xF5 reports status of HPD. This register is provides status of HPD. This register is only useful if HPD is enabled (register 0x5C bit 0 (HPD_DISABLE) is cleared).

    Address 0xF6 thru 0xF7 report errors associated with DSI to DP video timing. Typically, errors are set in these registers when video timing programmed into DSI86 doesn’t match timing received on the DSI interface. It is important the DSI86’s video registers located from 0x20 thru 0x3A match video timing used by the DSI source. The DSI86 will derive the DP timings from values programmed into these registers.

    It also looks like link training is failing. Have you used the DSI86 register calculator tool to generate the CSR values?

    2451.SN65DSI86_PANEL_VIDEOREGISTER_CALC.xlsm

  • 0 in reply to Vishesh Pithadiya
    Prodigy 10 points

    Hi ,

    Thanks for your reply.

    First of all, the timing calculator you attached is already applied and is causing problems.

    0x20 to 0x3a are set to match the DSI timing of the calculator and SOC below.

    " Address 0xF5 reports status of HPD. This register is provides status of HPD. This register is only useful if HPD is enabled (register 0x5C bit 0 (HPD_DISABLE) is cleared). "  <==   Does it mean that I need to Clear 0x5C? Or does it mean that I should use it by disabling HPD?

    Below is the result after HPD_DISABLE.

    The special part is that if you use "0xA" of 0x96, the Color bar is not output, but if you set 0x96 to 0x1, the Color bar is output.

    1. Timing calculated with 2451.SN65DSI86_PANEL_VIDEOREGISTER_CALC.xlsm

    However, if you use script NoASSR, the following error occurs.

    2. MIPI DSI timing of SOC.

    3. The waveforms below show that the DSI HACT and HTOTAL values ​​output from the measured SOC are similar to the calculated values ​​at 1080p 60.

      

      a. HACT

    b. HTOTAL

  • 0 in reply to kisung park
    TI__Mastermind 38090 points

    Hi,

    You need to toggle the value in this for the edits you have made to the spreadsheet.

  • 0 in reply to Vishesh Pithadiya
    TI__Mastermind 38090 points

    The register calculations are incorrect. The reason the colorbar works is that the lower resolution is being scaled to the monitor. Actual mistimed data will not be able to do this.

  • 0 in reply to Vishesh Pithadiya
    Prodigy 10 points

    "You need to toggle the value in this for the edits you have made to the spreadsheet. "

     ==> Are you referring to the part below?

    What should I refer to the table in this section?

    I don't know much about the DP output part, so please help me.

  • 0 in reply to kisung park
    Prodigy 10 points

    The table size for EDID of SN65DSI86_PANEL_VIDEOREGISTER_CALC.XLSM is larger than (16 X 8) the EDID value extracted from the monitor is (32X8). Should I input only some of the data?

    1. 1. EDID extracted from the monitor (32 X 8)

    2.EDID that can be placed in SN65DSI86_PANEL_VIDEOREGISTER_CALC.XLSM

  • 0 in reply to kisung park
    TI__Mastermind 38090 points

    Hi Kisung,

    The calculator tool uses the data provided in two ways.

    1) Fill the chart (orange inputs) and calculate the register values using this information

    2) Fill in EDID and calculate register values using that.

    I recommend using the chart as you are able to fully understand what you are inputting. 

    Toggling "EDID inputs in Datasheet Table" tells the spreadsheet that the display data is inputted in the chart and not pulled from the EDID matrix. One easy way to confirm that the display information inputs are valid is to see the minimum DSI clock rate, # of DP lanes, and optimum datarate. 

    It seems that the spreadsheet is configured properly in the last picture you sent.