TCAN4550: Communication error.

Hello Kengo,

Communication errors at higher temperatures are usually associated with a drop in the overall capacitance load on the crystal which causes the peak-to-peak amplitude of the waveform to increase.  This in turn causes the lowest level (min voltage) of the waveform to drop low enough to trip the comparator that is used to determine whether the OSC2 pin is "grounded" at startup which instructs the device to operate in single-ended clock mode instead of the crystal mode.  If the device switches to single-ended mode, there will not be a proper clock for the digital core or MCAN controllers and SPI and CAN communication can be disrupted.

The solution is to make some optimizations to the crystal clock circuit that will create some margin in the OSC2 waveform voltage levels and ensure stable operation.

The recommended solution is to add or increase the value of the series dampening resistor that is between the OSC1 pin and the crystal.  This resistor will reduce the amount of current reaching the crystal and "dampen" or reduce the amount of mechanical vibration and the corresponding waveform voltage.  Common values are between 10 and 100 ohms.

If there is not a series resistor between the OSC1 pin and the crystal, then increasing the value of the load capacitors on the crystal will reduce the drive level and add the needed capacitive margin for the drop in parasitic capacitance that comes from a temperature shift.  2-4pF of increase usually suffices.

Please see the TCAN455x Clock Optimization and Design Guidelines Application Report (Link) for more information.

Regards,

Jonathan