Tool/software:
Hello,
This device can operate in either/or duplex setting, depending on the appropriate auto-negotiated setting.
Please see the setup and hold time for TX and RX clock specification for RGMII in datasheet.
Which modes are you interested in understanding what impact is being had on simulation?
Sincerely,
Gerome
Hi Gerome,
Thanks for clarifying the points...
I am interested in exciting maximum signal activity in the system. Does full-duplex mode specify activity on TX and RX busses in parallel?
Hi Usman,
Full duplex indicates that both MACs can send data irrespective of whether or not the other MAC is sending data. This is different than half duplex where communication will only act in one direction at a time.
Sincerely,
Gerome
Hi Gerome,
I hope the full duplex that you are referring here is along with SoC and PHY DP83867IR.
I am also looking at the timing diagram of each signal mentioned below and how does these signals affect in full duplex mode. Since I am planning to simulate PHY chip I would like to understand the parameters to be considered for full duplex.
The pin no's and names are:
Pin no. 33 - RX_D0
Pin no. 34 - RX_D1
Pin no. 35 - RX_D2
Pin no. 36 - RX_D3
Pin no. 32 - RX_CLK
Pin no. 38 - RX_DV/RX_CTRL
Pin no. 28 - TX_D0
Pin no. 27 - TX_D1
Pin no. 26 - TX_D2
Pin no. 25 - TX_D3
Pin no. 29 - TX_CLK
Pin no. 37 - TX_EN/TX_CTRL
This is taken from DP83867IRRZ datasheet.
Thanks,
Usman
Hi Usman,
The MAC signals have less of an impact on full duplex mode. This ideally should be dependent on the MACs to understand if the bus is busy (via RX_DV) as well as the PHYs to set duplex communication accordingly. Each MAC pin is unidirectional.
Sincerely,
Gerome