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Original question:

DP83869HM: Is CLK_OUT capable of generating 125MHz from internal PLL?

DP83869HM: 25 MHz or 125 MHz for 1000Mbps, does it matter?

Jennifer Bernal
Genius 17045 points
Part Number: DP83869HM
Other Parts Discussed in Thread: LMK05318B, AM625,

Tool/software:

Hello ePHY team,

I am figuring out the connections for the AM625, DP83869HM, and LMK05318B. Other on-going thread:  LMK05318: Sync E Hardware connections understanding and Reference.

For a 1000 Mbps Ethernet use case, it is clear that the clock rate must be 125 MHz between the AM62 and the DP83869HM.

However, for the recovered SyncE clock between DP83869HM and LMK05318B, does it matter if either 25 MHz or 125 MHz is picked for CLK_OUT when using 1000 Mbps? Since the recovered SyncE clock provides the frequency accuracy, I don't see why it would matter what frequency is fed into the network synchronizer (LMK05318B).

Thank you,

Jennifer

Applications Engineer

Clocks and Timing Solutions

  • 0
    TI__Mastermind 32455 points

    Hi Jennifer,

    This would depend on what the network synchronizer is using the clock for. From the PHY perspective, we are only concerned with outputting the recovered clock from the data link.

    If the network synchronizer only needs a 25MHz CLK, then that would be ok from the PHY standpoint.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    TI__Genius 17045 points

    Hi Shane,

    Thanks for clarifying. In that case, 25 MHz or 125 MHz into the network synchronizer does not matter because the synchronizer will output 25 MHz to the PHY clock (XI pin) regardless of the network synchronizer's input frequency.

    Regards,

    Jennifer