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DS90UH947-Q1: DS90UH947-Q1

?? ?
Prodigy 20 points

Part Number: DS90UH947-Q1

Audio is being transmitted us ing DS90UH947 and 948, with the audio format being TDM 4*4 and FS at 48 kHz.

Please check the attached circuit diagram to see if there are any issues.
TX.pdfRX.pdf
Also, if video is not transmitted, is it possible to transmit only audio? Please confirm. 

  • 0
    TI__Mastermind 24835 points

    Hi Guotao Ding,

    Will check these schematics for you. Clarification requested for your application:

    ?? ? said:
    Also, if video is not transmitted, is it possible to transmit only audio? Please confirm. 

    You mean, if SoC is not sending video data but the Audio is still being sent to the I2S pins?

    I2S is part of the forward channel transmission frame, so if the forward channel is disabled the audio transmission will not reach DES. However, if the forward channel is not disabled and the video is just filler (blank screen, black screen / null data) then the FC can still be active just sending empty video frames, and the additional signals can still be sent over.

    Please let me know if this understanding was correct.

    Best,

    Miguel

  • 0
    Prodigy 20 points

    As drawn on the circuit diagram, I haven't connected the hardware for transmitting video. Is it possible to transmit only audio like this? Can I just enable the video-related registers? Please help me confirm.

  • 0 in reply to ?? ?
    TI__Mastermind 24835 points

    Hi Guotao,

    I am double-checking internally for your specific question; whether I2S data can be passed onto the forward frames to the 948 without incoming video. Thanks for your patience.

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    TI__Mastermind 24835 points

    Hi Guotao,

    In 94x, no video is required since I2S is transmitted via FC GPIO frames. However, internal CLK or an external clock may still be needed to drive the forward channel of the link.

    Is there a clock intended to drive the 947 side?

    In the absence of PCLK, the device will automatically configure to the internal OSC (can check register 0x03[1] is enabled to ensure this happens).

    This may be able to drive the forward channel frames for GPIO and I2S and I2C. Please let me know if you have any further questions.

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    Prodigy 20 points

    ご丁寧にご回答いただきありがとうございます。ご回答の通り、947と948は外部クロックやビデオ信号をキャリアとして依存することなく、オーディオおよびI2C信号を伝送することが可能です。それでは、お手数ですが947と948の回路図が正しいかどうかをご確認いただけますでしょうか。947と948の回路図は最初のメールに添付しました。問題があれば、早めにご連絡ください。よろしくお願いします。

  • 0 in reply to ?? ?
    TI__Mastermind 24835 points

    Hi Guotao,

    I will take a look into these circuits internally and determine if there is any issue with the configuration. Thanks for your patience.

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    TI__Mastermind 24835 points

    Hi Guotao,

    While the device can default to the internal clock in order to drive the FPD-Link, the only concern is stability of the CLK. Since the clock was only intended to be used for built-in self-testing purposes, it may have some variance of +/-10% or greater. Let me know if you think this is a concern for your transmission.

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    Prodigy 20 points

    ご回答ありがとうございます。内部CLKの発振周波数はいくつですか。私の音声伝送周波数は6.144MHzですが、±10％の偏差がある場合、影響を受けますか。

  • 0 in reply to ?? ?
    TI__Mastermind 24835 points

    Hi Guotao,

    Internal CLK frequency is determined by register 0x14[2:1], specifically:

    "OSC Clock Frequency in Functional Mode when PCLK is not present and 0x03[2]=1.

    00: 50MHz Oscillator

    01: 50 MHz Oscillator

    10: 100 MHz Oscillator

    11: 25 MHz Oscillator"

    I am not certain if the signal quality would be affected given the frequency variations, I would need more time to look into this internally.

    Thanks,

    Miguel

  • 0
    Prodigy 20 points

    そちらで上記のアプリケーションの回路図の確認はどのようになっていますか、問題はありますか。返信をお願いします。

  • 0 in reply to ?? ?
    TI__Mastermind 24835 points

    Hi Guotao,

    From the schematic, the configuration is theoretically possible if using the internal clock output instead of a referenced clock from the LVDS input. However, this configuration is not validated since this is not one of the considered use-cases for the devices, so there is not verification that the I2S audio is unaffected unless there is a given CLK.

    Other than this, there are not any other violations of the device configurations.

    Please let me know if you have any further questions.

    Best,

    Miguel