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AM6421: AM6421 — GPMC Multi-Device Configuration (CS0, CS2, CS3) — Software Driver Support and Timing Concerns

Harshith SB
Prodigy 30 points

Part Number: AM6421
Other Parts Discussed in Thread: SYSCONFIG

Device: AM6421
SDK Version: MCU+SDK 12.00.00.07.04 (Released: 14 Apr 2026)
SysConfig Selection: Non-Multiplexed 16-bit NOR — Asynchronous
Tool: SysConfig + CCS
Core: R5F (primary application core)

Hi TI Team,

We are currently developing a custom board based on the AM6421 SoC and are using the GPMC interface to connect the following devices:

1. FPGA — Microsemi Igloo2 M2GL090-FG676
   - Connected on CS0 and CS2 (two separate address regions mapped to internal FPGA logic blocks)
   - Interface: Non-Multiplexed 16-bit NOR Asynchronous

2. NV_SRAM — Cypress CY14B116N-ZSP25XI (1M × 16-bit, 25ns)
   - Connected on CS3
   - Interface: Non-Multiplexed 16-bit Asynchronous SRAM

All three chip selects (CS0, CS2, CS3) share the common GPMC address, data (16-bit), OE, WE, and BE lines. Each device is differentiated by its assigned chip select and address space in the GPMC memory map.

We have reviewed the following FAQ:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1349234/faq-am24x-am64x-am62x-what-are-the-maximum-sizes-of-nand-or-nor-or-psram-memories-that-can-be-connected-to-gpmc-for-the-am24x-am64x-am62x

Queries:

Q1. Since MCU+SDK does not have a dedicated driver for an asynchronous NOR-type FPGA interface or an nvSRAM, is the GPMC Low Level Driver (LLD) the recommended approach for implementing custom device drivers for CS0, CS2, and CS3 independently?

Q2 — Multi-CS Bus Reliability in Asynchronous Mode

The FAQ states:
"If the user intends to connect different memory devices on separate chip select lines, this may increase bus capacitance and not allow GPMC to work reliably."

We understand this concern from a signal integrity perspective. However, we would like to clarify whether this warning applies equally to Asynchronous mode as it does to synchronous or higher-frequency configurations.

In our case, we are operating in Asynchronous NOR mode. Are there specific derating guidelines (e.g., recommended guard cycles, minimum OE/WE pulse width adjustments) when multiple devices share the GPMC bus across CS lines? Or is the warning regardless of operating mode?

Q3 — Known Silicon Errata or SDK Limitations on CS2 and CS3

The FAQ and SDK examples predominantly reference CS0 for validation. We are using CS2 and CS3 in addition to CS0.

Are there any known silicon errata on the AM6421 or known SDK limitations (as of MCU+SDK 12.00.00.07.04) specifically affecting CS2 or CS3 

Q4. For the nvSRAM (CY14B116N), since it is a standard async SRAM interface, would a memory-mapped read/write approach (volatile pointer access) over GPMC be functional and safe, assuming correct timing register configuration?

Thank you for your support. Please let us know if any additional information is required.

Regards,
Harshith
Phytec

  • 0
    TI__Guru 54928 points

    Hello Harshith,

    I have shared the steps below to enable GPMC on different CS lines, and you can check the last comments in the e2e below.

    There, I have explained the configuration for two CS lines, and you can make similar changes for three CS lines.

     AM2434: GPMC use two CS signals 

    We have not performed testing on other CS lines, and our EVM is mainly connected to CS0. Based on the test results, we discussed this in the FAQ.

    There are no errata on CS2 and CS3, and you can still use CS2 and CS3 the same as CS0.

    Signal integrity concern remains: Multiple devices sharing GPMC_A[n:0], GPMC_D[15:0], GPMC_OE, GPMC_WE, and GPMC_BE lines increase capacitive loading.

    Lower risk because there's no clock synchronization requirement between devices—timing is controlled by open-loop control signals (OE, WE, BE, CS).

    We have not tested this pattern, and my suggestion is to raise a new e2e for the specific use case of GPMC so that hardware experts can provide proper HW design recommendations.

    The PSRAM and NOR memories are memory-mapped to the SOC, so you can perform read and write operations.

    Regards,

    Anil.