Part Number: DS110DF410
Dear Team,
We are following up on the status of our previous inquiry. The following technical issues remain unresolved and are impacting our current development timeline.
1. EEPROM Mapping and Register Verification We require the procedure to read back active register values from the Retimer. Currently, after the EEPROM load sequence completes (indicated by All_done transitioning Low), the channel registers do not reflect the expected data.
Please provide the specific methodology for EEPROM data writing and file generation to ensure correct internal register mapping.
2. SGMII Master Mode Functionality While we have successfully verified SGMII throughput in Slave Mode, the performance is not being replicated in Master Mode. We need a definitive solution or a configuration adjustment to ensure Master Mode is fully operational.
We look forward to your prompt technical feedback to resolve these discrepancies.
Request references: E2E1635901 & E2E1633420
Thanks,
Veeramanikandan S