Both LMH1982 and LMH1983 have LVDS clock outputs.
These output clock may be DC coupled to differential inputs of FPGAs with 2.5V power rail.
My concern is that if LVDS output may higher than 2.5V signal during the power up and down transition time.
Please let me know if the LVDS outputs of LMH1982 and LMH1983 never output higher than 2.5V signal
even if its power on/off tangent instance.
Mita