Hello,
I am using the SN65LVDS93 to serialize 28 LVCMOS33 signals coming from the Spartan 6 FPGA. I am sending to the SN65LVDS93 a video pattern. I am having some problems with the serialization. The LVDS outputs seem to be reseting. However the SHTDNz signal is steady at 3,3V.
The output stays at 0V during 4us (which is odd, because LVDS goes from 1v TO 1.4v), and then goes to 1V and increases its value up to 2V, and then goes to 0V again and repeats the sequence.
Strangely, the clock seems to be correctly transformed to LVDS.
The clock is at 50Mhz.
PLVCC, VCC, IOVCC[1:0] and LVDS_VCC are at 3,3V
It could be a coincidence but the enable time (after SHDNz rising edge) in the datasheet is at 6 us.
Thank you!
