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SN65LVDS93 Problem

Other Parts Discussed in Thread: SN65LVDS93

Hello,

I am using the SN65LVDS93 to serialize 28 LVCMOS33 signals coming from the Spartan 6 FPGA.  I am sending to the SN65LVDS93 a video pattern. I am having some problems with the serialization. The LVDS outputs seem to be reseting. However the SHTDNz signal is steady at 3,3V.   

The output stays at 0V during 4us (which is odd, because LVDS goes from 1v TO 1.4v), and then goes to 1V and increases its value up to 2V, and then goes to 0V again and repeats the sequence.

Strangely, the clock seems to be correctly transformed to LVDS. 

The clock is at 50Mhz.

PLVCC, VCC, IOVCC[1:0] and LVDS_VCC are at 3,3V

It could be a coincidence but the enable time (after SHDNz rising edge)  in the datasheet is at 6 us.

Thank you!

  • When sending 0V to all de 28 LVTTL input signals , the SN65LVDS93 outputs 0V in the LVDS outputs.

    When inputing 3,3V in all the 28 LVTTL input signals, the SN65LVDS93 outputs 2,9V in all the LVDS outputs.

    This is weird. How the SNLVDS93 is able to output 2,9V?

  • Hello,

    It seems that you already verified all the power rails are valid as well as CLKIN, Have you discarded a damaged device?

    Are you placing 100ohm differential loads on the LVDS outputs?

    Can you send your schematics?

    The device can output up to Vcc+0.5V.

    Toggle SHTDN low and high after CLKIN is valid.

    Regards 

  • Hello,

    The problem was the 100 ohm differential load. Now that I have placed them everything works fine.

    Thank you,

    Regards