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TPD12S016 Usage

Kishore Bachina
Prodigy 60 points
Other Parts Discussed in Thread: TPD12S016, TFP410, TFP401A

Hi 

I am Using TPD12S016 ESD device in both DVI transmission and receiving. ( i.e. between DVI Connector and TFP401A, as-well between DVI Connector and TFP410). Is this OK.

Another question is whether TPD12S016 data (high speed i.e. Data 0+/- to Data 2+/- )  and clock  signals have internal pull ups ?.  because , while signal integrity analysis, If i am using 50 ohm pull up on these lines, video signal quality is good else not good.

please help me in this regard.

regards,                                                                                                                                                                                 Kishore.

  • 0
    TI__Mastermind 31655 points

    Hello Kishore,

     

    The TPD12S016 will work equally well on both the transmitting and receiving ends of your DVI signal chain.

    The the Data 0+/-, Data 2+/-, and the clock pins are purely ESD protection diodes, and have no internal pull up resistors.

     

    Regards,

  • 0 in reply to Scott Cummins
    Prodigy 60 points

    Hi Scott ,

    Thnaks for your response. I had one more query. 

    We are using TFP401A chip as DVI receiver on our card . TFP401A is driving RGB signals to FPGA. but while doing Signal analysis, the data lines and clock signals swing is limited to 2.5V instead of 3.3V at 162MHz. voltage swing is fine at 50MHz. but my frequency of operation is 162 MHz.

    can you help me where am I wrong, is it device limitation, or Layout issue or Simulation issue?. I am using IBIS Models provided by TI for simulation.

    regards,

    kishore.

  • 0 in reply to Kishore Bachina
    TI__Mastermind 31655 points

    Hello Kishore,

     

    The TPD12S016 will pass up to 3.4GBps (1.7 GHz) signals on the data lines. Could you provide your schematic and simulation file for us to better address your concern?

     

    Regards,

  • 0 in reply to Scott Cummins
    Prodigy 60 points

    Hi Scott

    please find the attachment for Simulation report and schematics.

    regards,

    kishore1411.Schematics.pdf7635.Simulation report.docx

  • 0 in reply to Kishore Bachina
    TI__Mastermind 31655 points

    Hi Kishore,

    Thank you for the documents. The TPD12S016 looks like it is hooked up just fine in the schematic.

    Could you run another simulation without the TPD12S016 in the path? If the voltage levels go all the way up to 3.3V, then try adding a 1pF capacitor in place of the TPD12S016. At that point if the voltage level goes back down, it may indicate that the capacitance budget has been exceeded for the system. Othewise, there may be a problem with the IBIS model that we have been unable to duplicate here.

     

    Regards,

  • 0 in reply to Scott Cummins
    Prodigy 60 points

    Hi Scott,

    Here problem is with FP_TFP1_DI0 net. which is driven by U27(TFP401A) and received by U1(FPGA). so can you explain how TPD12S016 chip will control the output of TFP401A. 

    we feel input signals for TFP401A are ok .which are driven by U29(MAX3845) Chip. corresponding nets are TMDS_D2+_FOR_YCC1, TMDS_D2-_FOR_YCC1 (all high speed TMDS inputs to tfp401a).

    one more query what should be the High speed TMDS signals voltage swing and what should be the differential termination we need to use for these signals.

    regards,

    kishore.

      

  • 0 in reply to Kishore Bachina
    Prodigy 60 points

    Hi Scott,

    This is continuation of TPD12S016 usage.  schematics.pdf  is the reference document for this query, which was sent in my early posts. 

    My task  is, I have to give the DVI input to the card and should get the same as output on P4 DVI connector.

    when I am giving DVI input to " P3"  connector, all data lines  and clock signals are brought to  3.3V.  before connecting to the DVI Connector which is on Card, I have checked the signals on DVI Connector, they were ok. I am using PC as my DVI Source.

    What could be the issue?

     

    regards,

    kishore.