Hi, does anyone know if I can use a SN65CML100 to convert LVPECL from a fiber receiver to 1.2 V CML for a Xilinx high speed serial transceiver. The interface has to be dc coupled so I need a level translator.
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Hi, does anyone know if I can use a SN65CML100 to convert LVPECL from a fiber receiver to 1.2 V CML for a Xilinx high speed serial transceiver. The interface has to be dc coupled so I need a level translator.
Hi Robert,
The SN65CML100 will support LVPECL to CML translation. Can you please describe for me what you mean by 1.2V CML to make sure that I am understanding your question correctly? Is 1.2V the termination voltage, differential swing? Thanks!
Sorry, FPGA input voltage swing is roughly .7V to 1.1V. Since the interface is DC coupled I am worried about the signal levels going above 1.2V.
Hi Robert,
IC. The SN65CML100 will provide you with the output levels that you require and if you would like to put some added protection between the SN65CML100 and the FPGA we can implement a termination network that would set the common mode level at a safe point. There is an IBIS model available for download in the SN65CML100 product folder which you can use to model the input and output circuits for your design. Please let me know if you have any additional questions?