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TLK105 phy will not complete auto-negotiation, no link established

T S1
Prodigy 30 points
Other Parts Discussed in Thread: TLK105

1

Hi, all - could use a hand from PHY experts

We are bringing up a new board with a TLK105 PHY.  We are successfully using MDIO to talk to it with Uboot drivers, but it will not establish link.

We have found that it continually oscillates the bit:

MDI-X mode as reported by the Auto-Negotiation state machine:
1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair)
This bit will be affected by the settings of the AMDIX_EN and FORCE_MDIX bits in the PHYCR
register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX
algorithm swaps between MDI and MDI-X configurations.

and sets the corresponding interrupt.  We have tried setting the Fast Auto, Link Loss Recover, and Robust options in the CR1 reg but no help.

This effect stops if we clear the Auto-MDIX enable bit in the PHYCR, but that doesn't help establish link.  Also, the Force option in PHYCR doesn't help.

It also tells us there is an Inverted Polarity and sets that interrupt as well, whenever we plug the other end of the cable into a receiving end.  This clears on a reset.

WThe effect is the same when we reverse the polarity of the lines in our cable.


What is the proper init procedure for this chip that will allow it to work correctly?


Reg dump:

U-Boot > mdio read FEC 0x0
0 - 0x3100
U-Boot > mdio read FEC 0x1
1 - 0x7849
U-Boot > mdio read FEC 0x2
2 - 0x2000
U-Boot > mdio read FEC 0x3
3 - 0xa211
U-Boot > mdio read FEC 0x4
4 - 0x1e1
U-Boot > mdio read FEC 0x5
5 - 0x0
U-Boot > mdio read FEC 0x6
6 - 0x4
U-Boot > mdio read FEC 0x7
7 - 0x2001
U-Boot > mdio read FEC 0x8
8 - 0x0
U-Boot > mdio read FEC 0x9
9 - 0x7cf0
U-Boot > mdio read FEC 0xa
10 - 0x104
U-Boot > mdio read FEC 0xb
11 - 0x0
U-Boot > mdio read FEC 0xc
12 - 0x0
U-Boot > mdio read FEC 0xf
15 - 0x0
U-Boot > mdio read FEC 0x10
16 - 0x5002
U-Boot > mdio read FEC 0x11
17 - 0x109
U-Boot > mdio read FEC 0x12
18 - 0x0
U-Boot > mdio read FEC 0x13
19 - 0xa00
U-Boot > mdio read FEC 0x14
20 - 0x0
U-Boot > mdio read FEC 0x15
21 - 0x0
U-Boot > mdio read FEC 0x16
22 - 0x100
U-Boot > mdio read FEC 0x17
23 - 0x21
U-Boot > mdio read FEC 0x18
24 - 0x400
U-Boot > mdio read FEC 0x19
25 - 0x8001
U-Boot > mdio read FEC 0x1a
26 - 0x10
U-Boot > mdio read FEC 0x1b
27 - 0x7d


Regards,

TS

  • 0
    TI__Mastermind 31600 points

    TS,

    I notice that some of the registers are not at their defaults.  One example is CR1 (address 0x0009) which is shown as 0x7CF0.  The upper bits (15:10) of this register are RESERVED.  Are you explicitly writing these bits or are these being set by the driver? 

    What is the link partner on the other end of the CAT-5 cable?  Is it also one of the new boards or is it a known good PHY?

    I would like to suggest running some new tests starting from a power up.  These tests would be run with a loopback cable so that the transmit signaling of the PHY is returned to the receive pins of the PHY.  The goal is to confirm that the PHY can link to itself. 

    Below is some information on how to create the necessary cabling:

      1. Cut a cable with about 1 foot of cable and the RJ45 connector
      2. Strip off about 3~4 inches of the outside plastic shield to expose the 4 pairs of twisted pair cable
      3. Bend back pairs 4/5 and 7/8 (these will not be used)
      4. Solder pair 1/2 to pair 3/6
            1. Solder wire 1 to wire 3
            2. Solder wire 2 to wire 6
      5. Now you have a loopback cable.
    Plug the cable into any operating 10/100 Ethernet port and link will be established (assuming Auto-Neg is enabled).  You can also force 100BASE-T or 10BASE-T full duplex to test those modes explicitly.

    With the loopback cable, I would like you to attempt link in the following configurations:

    1. Default configuration - Auto-Negotiation enabled (reg. 0x00 = 0x3100) and Auto-MDIX enabled (reg. 0x19 = 0x8001).
    2. Forced 100M full-duplex - 100M full-duplex enabled (reg. 0x00 = 0x2100) and Auto-MDIX disabled (reg. 0x19 = 0x0001).
    3. Forced 10M full-duplex - 10M full-duplex enabled (reg. 0x00 = 0x0100) and Auto-MDIX disabled (reg. 0x19 = 0x0001).

    For each of these cases, please check the following registers:

    • BMSR (address 0x01)
    • ANLPAR (address 0x05)
    • PHYSTS (address 0x10)
    • 10BTSCR (address 0x1A)

    I don't think a complete register dump will be necessary.  The key information should be available in these four registers.

    Patrick

  • 0
    Prodigy 30 points

    1

    Problem solved.  Turns out to be an indication that the wiring diagram you are looking at is inverted against what you would think.  Our HW designer got back to me about that this morning.

  • 0 in reply to Patrick OFarrell
    Prodigy 30 points

    1

    Thanks for the great suggestions Patrick.  I was just about to start working on it with the loopback technique.