Hello, I'm planning to use DP83640 as a core for clock and time distribution among several DAQ boards. I want CLK_OUT on these boards to be synchronized not only by frequency but by phase also. Suppose I have one board acting as master with GPS active for absolute synchronization and other boards acting as slaves.
Reading the DP83640 documentation I can’t clearly understand the CLK_OUT phase alignment capability and how CLK_OUT is related to internal PTP Clock (besides sharing rate adjustment logic).
What I see based on appnotes and datasheet itself (please, correct if something wrong):
1) CLK_OUT is synthesized separately from internal PTP Clock (although they share the same clock reference eg. external 25MHz CXO)
2) CLK_OUT is divided down from 250MHz (ratio from 2 till 255)
3) PTP Clock is a counter with a time base of 125MHz
4) CLK_OUT and PTP Clock share the same rate adjustment logic (it means that when we are tuning PTP Clock rate CLK_OUT follows this adjustment)
5) Step adjustment logic is related only to PTP Clock and it is simple increment/decrement of PTP Clock counter thus only the 8ns step matters to guaranteed roll to the next PTP counter value
6) There is no mechanism in DP83640 to directly trim output phase of CLK_OUT.
7) There is no mechanism in DP83640 to start CLK_OUT synthesis synchronously with a PTP Clock value
All step adjustments will influence the PTP Clock only, they won’t effect CLK_OUT. I have also tested it on my board: continuous 8ns stepping won’t affect the CLK_OUT.
But what does it mean at DP83640 datasheet page8: “Note that any step adjustment in the 1588 clock time will not be accurately represented on the 1588 clock output signal.”? It says that step adjustments may influence the CLK_OUT- How?
I thought if we want to phase align a CLK_OUT on master side to its PTP Clock (eg. we want the CLK_OUT rising edge be close to PPS) we must move a PTP Clock itself (using step adjustment logic) to the edges of CLK_OUT and there is no other way, right?. The accuracy of alignment will be +-8ns.
Now for slave CLK_OUT phase alignment. Suppose I’ve aligned CLK_OUT on master side, and a PTP is working: PTP Clock on slave side is closely tuned to PTP Clock on master side. All the step adjustments and rate correction that I do on a slave side is to closely match PTP Clock on a slave to the PTP Clock on master – how than CLK_OUT on slave will be phase aligned to CLK_OUT on master?
So what am I missing? What is a correct way to phase align a CLK_OUT on master and between master and slaves?