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Hi,
On customer boards, there are DS90UB925Q-Q1 and DS90UB927Q-Q1 for two different models. For these two devices, customer set the SCL Low Time register (0x19) with 0x00 to minimize the delay on I2C communication.
ADD(hex) | Register Name | Value (hex) |
0x19 | SCL Low Time | 0x00 |
However, it seems that this value potentially cause quite marginal I2C set-up time and I2C communication error occasionally. See example of waveform below.
Thus, I suggest customer to increase SCL Low Time value (not to use 0x00), however they have heard from TI that this SCL Low Time value includes time offset of 5 clock cycles(correspond to 200nS) which is necessary device to ensure the synchronization, even though they set this value to 0x00, minimum set-up still around 200nS.
Can you help me to understand how minimum set-up value with SCL Low Time can be calculated? Also it's helpfu , if you can share the guideline how to set this value correctly. Here is the table which I try to understand these values.
Internal Oscillator | 17.5MHz | 25MHz | 32.5MHz |
Variation | -30% (slower) | typical | +30% (faster) |
Unit Interval | 57.1nS | 40nS | 30.8nS |
Internal Time Offset (5cycles?) | 285.5nS? |
200nS? |
154nS? |
SCL Low Time (0x65: default) |
9421.5nS | 6600nS | 5082nS |
SCL Low Time | 285.5nS? | 200nS? | 154nS? |
Thank you for your help in advance.
Regards,
Ken