DS90CF386: Mapping to iMX6

Hi Shaun,

I reviewed your schematic, and I think there are some issues with the mapping. It looks like in the schematic that RxOUT0-27 just goes sequentially from LVDS_DATA0 to LVDS_DATA3. In reality, the deserializer does not output RxOUT0-27 sequentially from the LVDS outputs. The deserializer outputs are actually mapped as follows in the datasheet:

This diagram was originally taken from the DS90C385 serializer to show how the LVCMOS inputs are mapped onto the LVDS pairs, but this mapping also applies to how the serialized LVDS is mapped out of the DS90CF386.

Therefore, if you reference the DS90CF386 output bit-mapping, your mapping for RGB bits in the JEIDA format should be as follows:

Thanks,

Michael

Hello, I am working on a nearly identical application interfacing the iMX6 to the DS90CF386 but I am confused by this answer.  In the IMX6 LVDS mapping they encode the R-G-B data into the 7 "slots" for the Data0 to Data3 channels.  Are you saying that the Data_0 Slot 1 is output onto RxOUT6 and Data_3 Slot 5 is output to RxOUT_5?

Thanks in advance

Patrick

Hi Patrick,

Yes, that is correct. You must match up the RGB bit in the JEIDA slots with the corresponding RxOUT (or in the diagram, TxIN) bit that occupies the same slot position shown in Figure 10.

I agree with you that this is confusing, but this is an implementation that has long been in place by TI and other LVDS SerDes vendors. For more information, please see Application Note SNOA014. The mapping should match up with the listing in Table 1 of the app note.

Thanks,

Michael