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So first of all below is a better schematic of what we have for a circuit. The Host side goes to our FPGA, while the switched side goes to all of our SFP’s (we have 6 SFPs).
Attached pictures are from our O-Scope, I have both a view of the full 9 clock cycles and a close in view of the ACK bit. The pink is the SDA (sorry, I couldn’t find my good probe and the one I had was rather noisy, but it correctly shows the performance). So first the device was powered up and then reset, then we attempted to write the register to select one of the switches. So you can see the start condition, address and write bits are fine. During the ACK you can see the FPGA release SDA like it should after the 8th clock cycle, and then the TCA9548 tries to pull it low, but it seems to be having a hard time, and it only gets down to 1.0V. I guess I would suspect the resistor is too strong of a pullup, but I’ve never seen where 4.7k is too strong, that’s a pretty normal pullup for I2C. Note we’re running very slow, something like 63kHz.
thanks,
JJ