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TCA9548A: TCA9548A: mux channel selection issue / TCA9548A: i2c multiplexing problem

Part Number: TCA9548A
Other Parts Discussed in Thread: TPS65400

TCA9548A: mux channel selection issue / TCA9548A: i2c multiplexing problem

›Problem statement:
–TCA9548a selected mux’ed channel SCx / SDx is not getting toggled
–So not able to get the slave ACK from PMIC TPS65400 associated with that mux’ed channel
–Setup1: FTDI-PMIC direct
–Both TCA9548a and TPS65400 are connected directly to FTDI i2c master
–TCA9548a and TPS65400 give ACK
–No toggle observed in SC0 line
–Setup2: FTDI-PMIC via i2c mux
–TCA9548a is connected directly to FTDI i2c master and TPS65400 ia connected to SC0, SD0 line of TCA9548a (Tried connecting with SC1. SD1 channels also)
–TCA9548a gives ACK and NACK from TPS65400
–No toggle observed in SC0 line

Note: Board 1 contains i2c master and i2c mux (TCA9548a – 0x77), TCA9548a – 0x70 eval card is added to debug initial mux’ed channel not toggling issue

Attached with: schematic, setup diagram, scope captures

›Other specific actions carried out:
–SC0, SD0 lines pulled up with 10k in bread board
–Same tried with SC1, SD1 channels
Please recommend on power sequencing, bus / supply caps or reset if applicable
  • Hey Manikandan,

    I don't see an attachment here but I've seen this problem pop up about 3 times in the past week involving the FTDI dongle and our I2C switches.

    Here is an example where the customer's master is not properly sending a stop condition after the write transaction:

    Can you verify that in your o-scope shot. After sending the I2C address and write the byte, you issue a stop condition?

    Thanks,

    -Bobby

  • Hey Bobby,

    Thanks for the reply quick reply and link for expected scope pattern. Let me go through the link and issue i2c commands as required. As this is lock down scenario, it is taking little long time. Meanwhile, I'm attaching the schematics and captures as a zip file. 

    It would be great, if you can guide in specific direction

    ftdi_i2cmux_pmic.zip

    Thanks,

    Manikandan

  • Hey Bobby,

    I could check the channel selection write and see  'stop' bit from i2c master write. But the stop bit arises ~500uS after ack of slave channel sel write with ~5uS time interval between SCL rise and SDA rise. (Attached waveform is for reference)

    I would like to know,

    Is there any time restriction to emit a stop condition and will the SCx toggle on pmic ack on a valid stop condition

    Is it okay to focus only on achieving correct 'stop' condition 

    Thanks Bobby for the support,

    Manikandan

  • In scope capture, Ch3 shows as SC0 but actually it is probed on SC1.

    Same verified in SC0 as well by channel selection as 0x01

  • "Is there any time restriction to emit a stop condition and will the SCx toggle on pmic ack on a valid stop condition"

    The state machine of our device does not have an internal clock/oscillator so it does not actually know time. It is looking for a specific edge, That is while data line is low, clock rises, then data shortly after.

    "Is it okay to focus only on achieving correct 'stop' condition"

    After a valid right, yes.

    Please note, we need a valid write transaction followed by a stop condition. If you try to do a repeated start and then do a read and stop condition, the channel may not enable.

    Below, I went into detail in another post where I tried to recreate the stop condition from an FTDI dongle and showed that by modifying when I release the clock signal, I'm able to properly enable another channel even after 200ms of delay.

    -Bobby

  • Thanks Bobby,

    We are able to see the mux channels' toggling after configuring the STOP condition as you suggested. Though ack from PMIC (TPS65400) connected in associated mux'ed channel is seen, we see write issue in disabling write protect. Will carry out some experiment and acknowledge you on the result

    Hope, TPS65400 will acknowledge, write and read with the modified STOP configuration for i2c mux

    Attaching the screen capture If you can help on

    Ch1: SCL_in

    Ch2: multiplexed SDA

    Ch3: Multiplexed SCL

    -Manikandan