- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
Using DP83867IRRGZ on a custom board with Xilinx XC7Z045FBG676 FPGA.
The MDIO line seems to be getting pulled low by the PHY. I have a 2.2k pull-up to VDDIO, which is 2.5V. When PHY RESETN is low, MDIO is pulled high to 2.5V, as expected. Once PHY is taken out of reset, MDIO is being pulled low by something. When FPGA talks, Vhigh is only about 1.75V. When the PHY responds, Vhigh is only about 0.85V. When neither the FPGA nor the PHY are communicating, MDIO is pulled back low.
If I put PHY in reset and send out read requests from the FPGA, then the levels are correct.
What could be pulling MDIO low?
Here is an attempted read of PHY register 0x03:
Thanks,
Will
Will,
I found this as well on Xilinx's forum saying UG933 is incomplete. For LVCMOS standards you do not need VREF.
Have you tried floating VREF? I'd also like to see the MDC line to make sure the FPGA is giving the DP83867 32 clock cycles.
Have you also posted this question to the Xilinx forum?
Best Regards,
Rob,
It really looks like the problem does not concern VREF. I've attached two scope shots. The first one shows MDC and MDIO for attempted read of register 0x03 when the PHY reset is asserted low. Notice that the levels of MDC and MDIO are 2.5V, as they should be. The second image shows an attempted read of reg 0x03 when phy reset is high. Here, MDC levels are still correct, but MDIO is not pulled up to 2.5V. If MIO_VREF (or anything on the fpga side) were the issue, I would expect for the problem to persist even when phy is in reset.
There is another copy of this board, but I do not have it. I'm going to see if I can get someone to do the same tests on that board to make sure that it's not just the chip on this particular board.
Read of register 0x03 when phy in reset
Read of register 0x03 when phy not in reset
Thanks,
Will
