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TPS65982: HPD command Delay from HPD signal Input to TPS65982

Takashi Onawa
Genius 13200 points
Part Number: TPS65982

Hi Team,

My customer would like to know how long it will take for TPS65982 to receive the HPD signal and output it with the CC command in UFP use case.
Do you have any data on the delay?

Regards,

Takashi Onawa

 

  • 0
    TI__Mastermind 36751 points
    Hi Onawa-san,

    We are looking into this specification and will get back to you when we have an update.

    Thank you,
    Eric
  • 0
    TI__Guru 50120 points

    Hi Onawa-san,

    The total delay for the TPS65982 to receive the HPD signal includes both HW delay and FW delay. The two states where HPD occurs is from High to Low(unplug) and Low to High(plugged).

    Total for High to Low = 1.617ms

    Total for Low to High = 0.577ms  

    Regards,

    Jimmy Hua

    Consider checking the "Verify Answer" button if I've answered the question to your satisfaction.

  • 0 in reply to Jimmy Hua
    TI__Genius 13200 points
    Hi Hua-san,

    Thanks for your quick response on this and let me double check for my deep understanding.
    1. Are those time variable? or Constant?(For example, if TPS65982 get the HPD change under CC lines are busy, what's happened?)
    2. Are those time Max one? Or typ one?

    Regards,
    Takashi Onawa
  • 0 in reply to Takashi Onawa
    TI__Guru 50120 points
    Hi Onawa-san,

    Let me look into this with the test engineer and get back to you once I get any updates.

    Regards,
    Jimmy Hua
  • 0 in reply to Takashi Onawa
    TI__Guru 50120 points

    Hi Onawa-san,

    To be more specific, the HPD have a HW and FW latency. Below is a breakdown of the two type of delays:

    A. HW state machine delay + interrupt latency (time from HPD change until FW enters interrupt service routine)

    B. FW latency (time from interrupt service routine start to PD message starts)

     

    “A” can change based on different HW state machine delays which can be calculated.

    “B” seems to be fixed at 217 us for a typical case.

     

    For High to low transition I see A=1.4 ms

    For Low to High transition I see A= 0.36 ms

     

    Total for High to Low 1.617 ms

    Total for Low to High 0.577 ms

     To answer your question:

    1. The time calculated can be variable depending on the HW delays. The FW delay seems to be consistent at 217us(typical).

    2. Those time values are for typical use cases.

    Regards,

    Jimmy Hua

  • 0 in reply to Jimmy Hua
    TI__Genius 13200 points
    Hua-san,

    Thanks for the detail. I understood .

    Regards,
    Takashi Onawa