Other Parts Discussed in Thread: LMH1981
We use a lmh1982 as clock source and TOF for our FPGA system.
A trilevel sync signal with is with a LMH1981 sync separator delivers H and V sync.
We are doning HD and Full HD, progressive, interlace and fractional.
The problem:
We see ~10% of random locks.
All programming is done acording to the manuals.
We did additional tests and improved the locking by adding longer "delays" to the init phase.
According to the manual, after setting up the PLL 1 parameters and activating genlock one has to wait until PLL 1 is locked and then continue with the initialization sequence.
To check the PLL 1 status, the second bit of the status byte of the genlock chip is evaluated.
This procedure does not seem to be 100% stable, since I needed to add a delay of at least half a second after the PLL 1 check to avoid "random locking" to arbitrary lines.
Additionally I had to increase the wait time during the initialization sequence (after setting EN_TOF_RST and TOF_INIT registers to 0) from one frame to at least 200 ms.
We always get a stable clock, but with ~5% we got a random TOF postion.
What must be done to be 100% reliable for a lock?
