DP83848T: TXD pin be driven during power-on reset

Hi,

TIDM-DELFINO-ETHERCAT is TI Design for EtherCAT Slave. It uses two DP83822 with ET1100. ET1100 clock output (CLK25OUT1) is used as external clock source to X1 for two DP83822.

BECKHOFF document describes that pull-up/pull-down is added to X1 for DP83822. But pull-up/pull-down is not added to X1 in TIDM-DELFINO-ETHERCAT.

Is it allowed that X1 is floating during power-on reset? Or should pull-up/pull-down be added to X1?

Best regards,

Daisuke

Hi,

BECKHOFF document describes for DP83849:

Application Note PHY Selection Guide
https://download.beckhoff.com/download/document/io/ethercat-development-products/an_phy_selection_guidev2.5.pdf
"TXD is potentially driven by PHY before a clock signal is applied to X1 (ET1100/ET1200: CLK25Out cannot be used, an external clock source is required)."

In DP83849I datasheet, TXD3_A and TXD3_B seem to be output as strap pin.

Does DP83848T not have this issue?

Best regards,

Daisuke

Hi,

For DP83848T, our customer sees that TXD_2 pin is driven to 3.3V until reset is released after a power-up, once every about two times.

For DP83879I, a similar issue is posted here: http://e2e.ti.com/support/interface/ethernet/f/903/t/547298

Does DP83848T not have this issue? Is behavior of TXD pins unpredictable until a clock is supplied and reset is released?

Best regards,

Daisuke

Hi,

What is a workaround for the issue of driven TXD pins?

Should an external 2.2-kohm pull-up/pull-down resistor be added to X1?

Or should a clock be supplied to X1 before 3.3V power is supplied?

Best regards,

Daisuke