TUSB9261: recognition error by power up sequence

Shinichi Inoue

Guru 21626 points

Part Number: TUSB9261

Dear Specialists,

My customer is encountering recognition error at power up.

He conducted comparison experiments between TUSB9261 Demo Board and Customer's board.

From the results, it has a relationship power up sequence and waveform between VDD(1.1V core), VDD33V and VDDA33.

Could you please advise what is a problem and work around.

I appreciate your great help and cooperation in advance.

Best regards,

Shihichi

examination of TUSB9261 recognition error .pptx

over 8 years ago

0 Elias Villegas M. over 8 years ago

TI__Guru* 76130 points

Hello,
Can you provide the datasheet of the power regulator on the customer's board?
Can they reduce the ramp time of the VDD11 and VDD33 ?
The DEMO board has around 250us whereas the Customer's board has around 1ms

Regards

0 Shinichi Inoue over 8 years ago in reply to Elias Villegas M.

Guru 21626 points

Hi Elias,

Thank you for your reply.

(1)They are using EN5312QI(Altera)

(2) I'll make the customer try reduce the ramp time.

Could you please see attached file and confirm my understanding.

I appreciate your great help.

Best regards,

Shinichi

reduce the ramp time.pptx

0 Elias Villegas M. over 8 years ago in reply to Shinichi Inoue

TI__Guru* 76130 points

Hello,

What I want to Customer to try is to reduce the ramp time of the VDD11 and VDD33, the pictures in your file show more like a "delay" time between the power rails.

Please look at below picture showing what I meant:

0 Shinichi Inoue over 8 years ago in reply to Elias Villegas M.

Guru 21626 points

Hi Elias,

Thank you for your reply.

I understand what you want the customer do.

I'll make them confirm and feedback.

I appreciate your great help.

Best regards,

Shihichi

0 Shinichi Inoue over 8 years ago in reply to Shinichi Inoue

Guru 21626 points

Hi Elias,

I could get the data you requested.

It could improve error rate.

And he has several questions, could you please advise?

Please see attached file.

---questions

1.When VDD11 rising time is faster, error rate is quite improved.

What reasons are considered?

2.Based on the results, it may be caused the slight difference at the start of the power supply.

How do you think of it?

3.According to the datasheet and errata, VDD11 needs to be rising up faster or simultaneously, what is the point starting point of rising or certain voltage.

In this case, could you provide what is the voltage.

The template is helpful

4.The timing of DEMO Board, VDD11 is rising when VDD33 is rising, is there any problem?

---

I appreciate your great help and cooperation.

Best regards,

Shinichi

examination of TUSB9261 recognition error（２） .pptx

0 Elias Villegas M. over 8 years ago in reply to Shinichi Inoue

TI__Guru* 76130 points

Hello,
1. In general you can't have neither a very slow ramp nor a very fast, the first one will cause indeterminate states and the second one will cause large overshoot, this is not related only to the TUSB9261 but to any given digital circuit.
2. Yes, you have to meet the power up requirements.
3. VDD and VDD33 can start simultaneously, or VDD can start before VDD33 (10us), if you can't ensure that VDD starts simultaneously of before VDD33 then you have to make sure GRSTz is asserted until both power rails are stable.
4. No problem.

0 Shinichi Inoue over 8 years ago in reply to Elias Villegas M.

Guru 21626 points

Hi Elias,

Thank you for your reply.

I sent your answer to the customer.
If they have an additional question, I consult you again.

I appreciate your great help.

Best regards,
Shinichi

0 Shinichi Inoue over 7 years ago in reply to Shinichi Inoue

Guru 21626 points

Hi Elias,

I am confirming your comment and have a question.

Could you please advise?

According to your answer3, VDD can start before VDD33(10us).

Where does 10us spec come from?

I couldn'f find any document, (datasheet, application note etc)

---

3. VDD and VDD33 can start simultaneously, or VDD can start before VDD33 (10us), if you can't ensure that VDD starts simultaneously of before VDD33 then you have to make sure GRSTz is asserted until both power rails are stable.

I appreciate your great help.

Best regards,

Shinichi

0 JMMN over 7 years ago in reply to Shinichi Inoue

TI__Guru 60870 points

Hello Shinichi,

Can you confirm the GRSTz timing on the customer design? Power ramp sequencing should not have an effect on the device performance as long as GRSTz is held low for 2 ms after the power rails are valid.

Regards,
JMMN

0 Shinichi Inoue over 7 years ago in reply to JMMN

Guru 21626 points

Hi JMMN,

Thank you for your reply,

I'll share this information with the customer.

I appreciate your great help.

Best regards,
Shinichi

0 JMMN over 7 years ago in reply to Shinichi Inoue

TI__Guru 60870 points

Hello Shinichi,

Is there any further update from the customer?

Regards,
JMMN

0 Shinichi Inoue over 7 years ago in reply to JMMN

Guru 21626 points

Hi JMMN,

Thank you for your reply.

I'll confirm the customer and then feedback.

I appreciate your great help and cooperation.

Best regards,
Shinichi

0 JMMN over 7 years ago in reply to Shinichi Inoue

TI__Guru 60870 points

Shinichi,

I am closing this thread for now. If the customer has more questions, please post here to re-open the thread or start a new one.

Regards,
JMMN

0 Shinichi Inoue over 7 years ago in reply to JMMN

Guru 21626 points

Hi JMMN,

Thank you for your reply.

I understand this thread close.

If the customer has an additional information, I'll consult you again.

I appreciate your great help and cooperation.

Best regards,

Shinichi

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TUSB9261: recognition error by power up sequence