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DP83867IR: RX_CLK frequency problem in loopback mode

lime lab
Prodigy 20 points
Part Number: DP83867IR

Support Path: /Product/Development and troubleshooting/Search the forums for my problem/

In 100MBit RGMII Phy loopback mode, RX_CLK frequency spontaneously drop to 0 Mhz and than rising to 2.5MHz and than continously rising to 25MHz, Autonegotiation is turned off, and MDIO accesses is off.

Our frame traffic speed is 84MBit. When RJ45 cable with loopback inserted ( RX->TX) frequency is stable when phy still in loopback operation mode. Is there any solution of this problem

  • 0
    TI__Mastermind 26320 points
    Hi,

    Your description of problem is not very clear to me. Can you please help writing step by step both cases where frequency is stable and where frequency is not stable.

    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 20 points
    Hi, Geet

    In both cases devices register set to loopback mode (14 bit of BMCR [0x0000] is set) , when nothing inserted in RJ45 slot RX_CLK frequency spontaneously drop down and then rise to 2.5 and than to 25 Mhz continiously and this happens while data is sending.
    When RJ45 cable inserted with loopback this means in cable RX connected to TX phy works stable.
  • 0 in reply to lime lab
    TI__Mastermind 26320 points

    Irresepctive of loop-back, when device does not have link with Link Partner, the clock on MAC interface is stepped down to lowest number to save powers. Once link-up is established with Link Partner, based on the speed negoitated on the link, MAC interface clock is adjusted. I believe that's what you are also observing.

    What you are trying to test with loop-back and debug ? 

    Regards,

    Geet