SN65LVDS93A: LVCMOS 3.3V parallel in to serialized LVDS 2.5V out

Hi Andre,

The differential signals are centered about 1.2V regardless if it is a 2.5V or 3.3V LVDS. The differential voltage goes from

0V to 2.4V. You can find more information at the link:

Regards,
Dennis

Hello Dennis,

thank you for the fast reply but I would like to add some information relating to my problem. The receiver of the LVDS signal is an "Xilinx Zynq 7020" placed on a ready designed module without any termination resistor at the Input.  This is the reason I have to use the internal termination of the "Zynq 7020". But the internal termination can only be used if the LVDS voltage matches the corresponding bank voltage.

The related user guide "UG471_7Series_SelectIO.pdf" of the "Zynq 7020" says:

"It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those
standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However, these criteria must be met:
• The optional internal differential termination is not used (DIFF_TERM = FALSE,
which is the default value)."

Is there any way to met this requirement using the "SN65LVDS93A" or something similar?

Regards,

Andre

Hello Dennis,

thank you for the fast reply but I would like to add some information relating to my problem. The receiver of the LVDS signal is an "Xilinx Zynq 7020" placed on a ready designed module without any termination resistor at the Input. This is the reason I have to use the internal termination of the "Zynq 7020". But the internal termination can only be used if the LVDS voltage matches the corresponding bank voltage.

The related user guide "UG471_7Series_SelectIO.pdf" of the "Zynq 7020" says:

"It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those
standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However, these criteria must be met:
• The optional internal differential termination is not used (DIFF_TERM = FALSE,
which is the default value)."

Is there any way to met this requirement using the "SN65LVDS93A" or something similar?

Regards,

Andre

Hello,
has anybody an idea how to met the above described requirement of the LVDS receiver?

Regards,
Andre

Hello Andre,

Actually, the SN65LVDS93A operates with a fixed common-mode output voltage of 1.2V and a differential output voltage that goes from a minimum of 250mV to a maximum of 450mV. Seems to be supported by your receiver.

Regards

Hello Joel,

thank you for your answer which helped me to understand the answer of Dennis. I think the post of Dennis already solved my problem but initially I was irritated by the "Nom of LVDSVCC= at 3.3V" in the datasheet of the SN65LVDS93 at page 7/ chapter 7.3.

Best Regards

Andre

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