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TCA9509: The step on the rising edge of SDA and SCL on BUS-A

Nick Dai
Expert 4240 points

Part Number: TCA9509
Other Parts Discussed in Thread: TCA9539

Hi Team,

   My customer meet an issue on TCA9509,the BUS-A was connected with a CPLD and there is no other device on BUS-A. As below figures shown,there is a step on every SCL rising edge of BUS-A. 

There was some setps on SDA rising edge of BUS-A also.

Could you help check the reason of the step and will these step impact the normal work of I2C?

Best Regards,

Nick Dai

  • 0
    TI__Guru* 81621 points

    Nick,

    This part (most buffers) have something similar to a static voltage offset on one side (this part has it on A side). It uses a small current source to monitor which side pulls low in order to avoid latching. You can read more about this here:

    ----------------------------------------------------------------------------------------------------------------------------------------------------------------

    The offset is about 200mV which seems like what you are seeing.

    Page 8 and 9 of the datasheet talk about this however there is an error (on our to do list to fix) of the figure titles being Bus A and Bus B (should be swapped).

    You will see when A side pulls low and gets pulled to Vol of A side transceiver. Then releases it will  then momentarily latch to the voltage offset before rising back to Vcca. When B side pulls low, A side will automatically get pulled to the offset voltage, then when released will jump back to Vcca. You can see this in figure 5:

    *note again this is the A side even though the figure states it is B side.

    This should not be an issue with I2C communication as this offset will be < 0.3*Vcca and should rise to Vcca in time for the transceiver to read the correct value of high.

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    TI__Expert 4240 points

    Hi Bobby,

       Thanks for your explanation.

       Could you help explain why there is a step in every cycle of SCL in A side during write operation?(CPLD write to PCA9509)

        The scope plot I have sent in past post.

    Best Regards,

    Nick Dai

  • 0 in reply to Nick Dai
    TI__Guru* 81621 points

    Hey Nick,

    I believe the reason is because you are pushing SCLB low then releasing. B side is still low for a short amount of time because it does not instantaneously get pulled back up to Vcc. So when A side releases and does not drive low, B side is now driving A low (causing that 200mV offset) for a short amount of time until it charges up to a point where TCA9539 sees B side has pulled high and releases A side.

    To summarize, B side is driving A low resulting in the voltage offset for a short time before B side charges itself up and releases A side. This because B side must rise first before A. B side likely releases after 0.3*VccB though depending on the internal circuitry it may even be 0.7*VccB.

    You can place a scope probe on SCLA and SCLB to check to see what B side is doing. At about what point do you see SCLB rise and release SCLA?

    If I am correct about the B side needing to reach a threshold value, then you can shorten the time A is latched low at the offset value by lowering the resistance value on B side. This will make B side's rise time faster and hit the threshold value quicker.

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    TI__Expert 4240 points

    Hi Bobby,

      Thanks for your explanation.

       The customer tested the SCLA and SCLB with two different pull up resistor value(4.7kohm and 2kohm) on SCLB. The step of 2kohm pull up was shorter than 4.7kohm pull up.

       But the question is the thresholds of SCLB for SCLA rising from offset value to high for 2kohm and 4.7kohm are different.

       Could you help check how to understand the threshold difference?

    4.7Kohm pull up

    2Kohm  pull up

    Best Regards,

    Nick Dai

  • 0 in reply to Nick Dai
    TI__Guru* 81621 points

    Hey Nick,

    "But the question is the thresholds of SCLB for SCLA rising from offset value to high for 2kohm and 4.7kohm are different.

       Could you help check how to understand the threshold difference?"

    I also believe the condition to release A side is not solely on the threshold value alone. There is likely two conditions that must be met and then fed into an AND gate. The second condition I am talking about is either a slew rate minimum must be met or an amount of time after the threshold is met it must be above this value for a certain amount of time. This is to make sure any oscillation or noise on the I2C bus does not accidentally release A side too early and cause signal integrity issues.

    The threshold voltages I talked about before should be constant and feed into a comparator. What you are seeing is a result of faster slew rate vs. slower slew rates. The faster slew rate is the 2.7k ohm resistor therefore it reaches a higher voltage before A side is released. (Lower resistance means faster pull up therefore faster slew rate)

    I suspect the time difference should be the same when they are released. (likely at 0.3xVccB)

    For example: if we say you must be above 0.3xVccB and for 15ns before we release A, then both points will release A at the end of 15ns but the voltage at which B side is at during the release will depend on the pull up resistor. For instance a larger pull up resistor like 4.7k will result in a lower voltage because it didn't slew as fast. Lets say after 15 ns it reaches 81% of it's final value when A is released. The opposite can be said with a lower resistor (2.7k for instance), after 15 ns it reaches 93% of it's final value because it had a faster slew rate.

    I hope this makes sense to you.

    You might be able to test this (assuming the second condition is time based) by moving the cursors to when B side reaches 0.3 x VccB and when A side releases. Check to see what the time difference is with the 4.7k and 2.7k. They should be close to each other.

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    TI__Expert 4240 points

    Hi Bobby,

      Thanks for your detailed explanation,I will check with customer for their test result.

    Best Regards,

    Nick Dai