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TLK10232: Optimization flow of TLK10232 HS

Roger Chang7
Prodigy 60 points
Part Number: TLK10232

Hi,

We met a problem very similar to

e2e.ti.com/.../649576

except that we use Xilinx's FPGA and we are currently stuck at the Pilot Run stage

Since Luis mentioned about "Unfortunately, these stage of "tuning" is exhaustive since user needs to sweep different values in different combinations for HS_SERDES_CONTROL_2 & 3, this process is automatic when Link Training is enabled but in 10GBASE-R this feature must be disabled."

We would like to know when should this manual Link Training process be proceeded?

Whenever the system is boot-up?

Whenever the fiber has been re-plugged?

Or we just need to proceed it once for one PCB design?

In addition, the fiber module may be changed for supporting both 10GBASE-SR and 10GBASE-LR.

Best Regards,

Roger Chang

ATEN INTERNATIONAL Co., Ltd.

  • 0
    TI__Genius 16150 points
    Hi Roger,

    The TLK10232 is intended to interface with backplane applications (10GBASE-KR). Although, this device is able to interface with SFP+ optical modules through the 10GBASE-R, since it uses the same PCS than 10GBASE-KR. When the TLK10232 is interfacing with optical modules, the Link Training and Auto-Negotiation should be disabled.
    Since the link training is disabled, the SerDes settings (HS_SERDES_CONTROL_2 & 3) have to be adjusted according the characteristics of the system, such as AC losses, length of trances, among others.

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Prodigy 60 points

    Hi Luis,

    Thanks for your reply.

    Let me express my understanding. In our application, the SFP+ module is assembled with our product in the manufacture process. Because there may have some characteristics variant between the combination of TLK10232 and SFP+ module, we should run the loopback BER test to adjust the SerDes settings (HS_SERDES_CONTROL_2 & 3) and save the best value in the DUT during our manufacture process. Is that correct?

    Regards,

    Roger

  • 0 in reply to Luis Omar Moran
    Prodigy 60 points

    Hi Louis,

    Any update?

    Regards,

    Roger

  • 0 in reply to Roger Chang7
    TI__Genius 16150 points
    Hi Roger,

    Sorry for the delayed response. The BER testing must be performed to adjust the SerDes settings according the characteristics of every system. Once, the optimal settings are gotten (0 error bit in HS_ERROR_COUNTER register), this test should be performed in several units to double-check the values of the registers involved to optimize the link. Then, these settings should be work for all the units in the same design.

    Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team