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DS25BR110: Output timing jump

Mark Guastaferro
Genius 11345 points
Part Number: DS25BR110
Other Parts Discussed in Thread: DS92LV18, DS25BR120

The DS25BR110 is being used to equalize/buffer a LVDS serdes signal after traveling over several meters of CAT5e cabling and output feeds into deserializer.

The following scope captures shows the serialized data coming into and output the DS25BR110. The scope is synchronized to RCLK of the deserializer.  Note that the input signals look similar, yet the output of the "bad" output has a 140 ps delay on the front edge. End of pulse timing is the same  This seems to be a binary occurrence, either it is correct or the pulse shortened by 140 ps.  

What would cause this discrete shift?.  The assumption is the equalizer operates as an analog filter, followed by an LVDS driver to restore the LVDS signal level and edge speed. 

  • 0
    TI__Mastermind 43795 points

    Hi Mark,

    I cannot be sure, but it seems you are measuring very close to the device input and output pins.  The BR110 equalizer is doing its job as the output edge is significantly sharper than the input edge.  It looks like there is some type of impedance discontinuity close to the DS25BR110 output. 

    What is the current equalization setting?

    What is the datarate?

    What is the input common mode voltage?

    The "bad signal" is narrower at the equalizer output. Just the TpLH seems to be different.

    The DS25BR110 should have a constant propagation delay from input to output.  

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    TI__Genius 11345 points
    Hi Lee,
    Thanks for the quick reply.
    The output of the BR110 is connected to a DS92LV18 serdes device with a very short interconnect. We are suspicious that the input capacitance of the LV18 is causing the hitch on the signal edges. I have been working with the LV18 team on this concern.

    For the BR110, the equalization setting is 0 for these plots. The LV18 is operating at 64MHz, so the serial data rate is 64x20 - 1.28 Gbps. A DS25BR120 is driving the signal across the CAT5e cable, so it should be setting the common mode voltage. Pre-emph is set to 0 for these plots. At the BR110 input, there is a 7.8k pull up to 3.3V on the P input and a 5K pull down on the N input to set a default logic state. If some pre-emphasis is added to the BR120, the data errors on the deserializer appear to be eliminated (Don't have plots of this condition).
  • 0 in reply to Mark Guastaferro
    TI__Mastermind 43795 points

    Hi Mark,

    There are two ways we may be able to tame that output glitch.

    1. Add a series resistor to both N and P signals at the DS25BR110 output.

    2. Add a parallel capacitor directly on the N and P signals right at the DS25BR110 output. 

    Have you tried to increase the input equalization to see if the pulse issue goes away?

    Regards,

    Lee

  • 0 in reply to Lee Sledjeski
    TI__Mastermind 43795 points
    Adding a 3pf capacitor eliminates the non-monotonic output waveform.
    Lee