Other Parts Discussed in Thread: TLK106, TLK105
Hi Rob,
original issue seems to be locked, so I provide update in this new issue.
I attached to the issue:
1) Quartz specs
2) Ethernet schematics
3) Register dump when PHY experience TX FCS errors
4) Register dump after power on
5) Register dumpo after reset
And below original problem description for reference.
Thanks for your help !
BR Oleg
======================================================
Hi !
We are using TLK106L as a PHY together with STM32F407 MCU. After several hours after PHY reset number of FCS errors for frames transmitted by PHY is rising from zero to 10-15% of total number of sent frames. After reset situation repeats, immediately after reset number of FCS errors on receiving side is 0 and then goes to 10-15%. Behaviour is the same with different models of ethernet switches.
PHY initialization sequence:
- write 0x8000 to reg0 (BMCR) - software reset
- small delay
- write 0x0000 to reg0 (BMCR) - set 10HALF mode (not really needed, caused by software structure)
- some delay
- write 0x1000 to reg0 (BMCR) - enable AutoNegotiation
- wait until Link established by polling reg1 (BMSR) bit 2(Link Status)
We are using external 50 MHz oscillator.
BR Oleg8054.ethernet.pdf1121.GEYER-KXO-V97-V2.pdf
Anchor s379 at office table
DUMP as errors mentioned, 2-3 hours after turned on
rare TX errors seen as
- UDP packets do not reach computer in same Ethernet segment (by device logs packets were sent)
- Telnet session pauses while printing from device a lot
phyreg *
[/lan/phyreg] Ethernet PHY regs:
PHY: TLK10xL
reg x0000=x1000
reg x0001=x786D
reg x0002=x2000
reg x0003=xA212
reg x0004=x01E1
reg x0005=x45E1
reg x0006=x0007
reg x0007=x2001
reg x0008=x0000
reg x0009=x7800
reg x000A=x0104
reg x000B=x1000
reg x000C=x0000
reg x000D=x0000
reg x000E=x0000
reg x000F=x0000
reg x0010=x0615
reg x0011=x0108
reg x0012=x6400
reg x0013=x2800
reg x0014=x0000
reg x0015=x0000
reg x0016=x0100
reg x0017=x0061
reg x0018=x0400
reg x0019=x8C01
reg x001A=x0000
reg x001B=x007D
reg x001C=x05EE
reg x001D=x0000
reg x001E=x0102
reg x001F=x0000
reg x0025=x0040
reg x0026=x0000
reg x0027=x0000
reg x003E=x0000
reg x003F=xB4FF
reg x0040=xC11D
reg x0041=x0000
reg x0042=x0000
reg x00AE=xA602
reg x00D0=x0006
reg x0155=x1F01
reg x0170=x0E52
reg x0171=xC85C
reg x0172=x5326
reg x0173=xFF1E
reg x0177=x189B
reg x0180=x0000
reg x0181=x0000
reg x0182=x0000
reg x0183=x0000
reg x0184=x0000
reg x0185=x0000
reg x0186=x0000
reg x0187=x0000
reg x0188=x0000
reg x0189=x0000
reg x018A=x0000
reg x0215=x000F
reg x021D=x0512
Anchor s379 at office table
DUMP after power-on
no TX errors seen by Telnet session after this dump
phyreg *
[/lan/phyreg] Ethernet PHY regs:
PHY: TLK10xL
reg x0000=x1000
reg x0001=x786D
reg x0002=x2000
reg x0003=xA212
reg x0004=x01E1
reg x0005=x45E1
reg x0006=x0007
reg x0007=x2001
reg x0008=x0000
reg x0009=x7800
reg x000A=x0104
reg x000B=x1000
reg x000C=x0000
reg x000D=x0000
reg x000E=x0000
reg x000F=x0000
reg x0010=x0615
reg x0011=x0108
reg x0012=x6400
reg x0013=x2800
reg x0014=x0000
reg x0015=x0000
reg x0016=x0100
reg x0017=x0061
reg x0018=x0400
reg x0019=x8C01
reg x001A=x0000
reg x001B=x007D
reg x001C=x05EE
reg x001D=x0000
reg x001E=x0102
reg x001F=x0000
reg x0025=x0040
reg x0026=x0000
reg x0027=x0000
reg x003E=x0000
reg x003F=xB4FF
reg x0040=xC11D
reg x0041=x0000
reg x0042=x0000
reg x00AE=xA602
reg x00D0=x0006
reg x0155=x1F11
reg x0170=x0E52
reg x0171=xC85C
reg x0172=x5326
reg x0173=xFF1E
reg x0177=x189B
reg x0180=x0000
reg x0181=x0000
reg x0182=x0000
reg x0183=x0000
reg x0184=x0000
reg x0185=x0000
reg x0186=x0000
reg x0187=x0000
reg x0188=x0000
reg x0189=x0000
reg x018A=x0000
reg x0215=x000F
reg x021D=x0510
Anchor s379 at office table
DUMP after software reset (hardware reset by pin of TLK106L)
no TX errors seen by Telnet session after this dump
phyreg *
[/lan/phyreg] Ethernet PHY regs:
PHY: TLK10xL
reg x0000=x1000
reg x0001=x786D
reg x0002=x2000
reg x0003=xA212
reg x0004=x01E1
reg x0005=x45E1
reg x0006=x0007
reg x0007=x2001
reg x0008=x0000
reg x0009=x7800
reg x000A=x0104
reg x000B=x1000
reg x000C=x0000
reg x000D=x0000
reg x000E=x0000
reg x000F=x0000
reg x0010=x0615
reg x0011=x0108
reg x0012=x6400
reg x0013=x2800
reg x0014=x0000
reg x0015=x0000
reg x0016=x0100
reg x0017=x0061
reg x0018=x0400
reg x0019=x8C01
reg x001A=x0000
reg x001B=x007D
reg x001C=x05EE
reg x001D=x0000
reg x001E=x0102
reg x001F=x0000
reg x0025=x0040
reg x0026=x0000
reg x0027=x0000
reg x003E=x0000
reg x003F=xB4FF
reg x0040=xC11D
reg x0041=x0000
reg x0042=x0000
reg x00AE=xA602
reg x00D0=x0006
reg x0155=x1F11
reg x0170=x0E52
reg x0171=xC85C
reg x0172=x5326
reg x0173=xFF1E
reg x0177=x189B
reg x0180=x0000
reg x0181=x0000
reg x0182=x0000
reg x0183=x0000
reg x0184=x0000
reg x0185=x0000
reg x0186=x0000
reg x0187=x0000
reg x0188=x0000
reg x0189=x0000
reg x018A=x0000
reg x0215=x000F
reg x021D=x0512
