We use the TCA6416 in our design. There is Tsp = 0-50ns in the datasheet. May I know why the TCA6416 define this spec? Since our CPU can’t accept this spec. Do you have any idea? Thanks
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Just to clarify, the TCA6416 is not recommended for new design and instead the TCA6416A is.
Tsp is a parameter that is defined in the I2C standard and indicates that all I2C devices need to have a glitch filter that can filter up to 50ns of spikes (this means our device also has this filter and can attenuate up to 50ns of spikes). ALL devices need to follow this spec to be I2C compliant. If you are expecting or need a larger glitch filter, there is an app note that discusses how to implement one:
Just to synchronize our project information beneath:
The expand IC we chose is TCA6416A, and our I2C clock is at a frequency of 99KHz,which belongs to the "standard mode" defined in the I2C protocol.
And my questions are listed as follow:
1) Refer to the I2C protocol, under the standard mode, there has no Tsp requirement which shown in I2C protocol as both high and low spec are NA.
Could we ignore this Tsp parameter since our measurement of Tsp is 280ns around ?
2) If our Tsp is so rough that exceed the requirement of a 50ns a lot, how can we inprove this spike to meet spec ?