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DP83867IRPAP-EVM: 100 Mbps Link up issues and data could not received on MAC

Part Number: DP83867IRPAP-EVM

Hello,

I am using DP86867IR as PHY interfacing with FPGA board and connected to PC on the other side. PC is configured to 100 Mbps full duplex communication. 

Following is the issue I am observing:

1. After reset through 0x1F = 0x8000; I see link going up and messages on the ethernet monitoring tool. Probably because Auto negotiation is activated and hence getting link up. 

But in case, Auto-negotiation is disabled after hard reset and try to set fixed rate of 100 Mbps, Link does not come up. Could you please let me know the possible root cause or proper sequence? 

2. How much time should I wait after Reset to access/modify the MDIO registers? From datasheet, I could conclude 200 ms, but for safe side I am putting delay of 500 ms before accessing MDIO registers to set fixed link rate. Is it okay? 

and the most important questions is:

3. After having link up, I can receive data on the MAC, but data transmitted from MAC are not shown on the Ethernet monitoring tool. 

For 10 Mbps link speed, I can see data on the tool. Can you guide me through to solve this issue? 

Please let me know, if you need any other information!

Thank you,

Hardik 

  • Hi Hardik,

    1. Is PC also configured for 100M Force Mode ? After disabling Auto-Neg on DP83867, you will need to trigger soft reset.

    2. 200 ms is good for DP83867.

    3. You may need to play with skew control between data and clock for RGMII. Refer to register 0x0032 and 0x0086.


    Regards,
    Geet
  • Thank you Geet for replying.

    1. Is PC also configured for 100M Force Mode ? After disabling Auto-Neg on DP83867, you will need to trigger soft reset.
    Hardik: I tried soft reset, but there are no attempt to establish the link.
    Is there any sequence recommended to initialise PHY? For example: First MDI relevant configurations, then MII relevant configurations etc..

    following is the sequence I am using:
    1) 0x1F = 0x8000 /** Hard Reset */
    /** Wait here for a while */
    2) 0x0D = 0x001F
    0x0E = 0x0031
    0x0D = 0x401F
    0x0E = (u32ReadData & 0x7F) /** Clear bit 7 of Configuration 4 register to configure strap RX_CTL; u32ReadData holds value stored @0x31 */ /** I decided to do this because no strap configuration on RX_CTRL and information from section 8.5.1 NOTE section */

    3) 0x00 = 0x2100 /** 100 Mbps, Full Duplex and Auto Negotiation OFF */
    4) 0x1F = 0x4000 /** As you recommended */
    /* I halt my debug session here, just to see if Link establishes and PC sends any data on the bus, but nothing happens. It remains disconnected */
    5) 0x0D = 0x001F
    0x0E = 0x0032
    0x0D = 0x401F
    0x0E = 0x0000 /** Disable RGMII */

    Do you see any error in sequence or any suggestions?

    3. You may need to play with skew control between data and clock for RGMII. Refer to register 0x0032 and 0x0086.
    Hardik: I am using MII interface and RGMII is also disabled correctly through Extended Addressing method.

    Thank you for your support!
    Hardik
  • Hi Hardik,

    Configuration to force 100M Force mode looks ok. Questions:

    1. If you enable Auto-Negotiation, does device links up ?

    2. Have you ensured PC is in force 100M mode as well ? Can you try connecting this to other device and ensure 100M force is supported by PC.

    BTW, why you want to force 100M, instead not use Auto-Neg ?

    Regards,
    Geet
  • Hi Geet,

    1. If you enable Auto-Negotiation, does device links up ?

    Hardik: Yes, it does. But Transmit from PHY to PC does not work. Receive works fine. 

    2. Have you ensured PC is in force 100M mode as well ?

    Hardik: Yes, in configuration settings, port is set to 100 Mbps Full Duplex. 

    Can you try connecting this to other device and ensure 100M force is supported by PC.

    Hardik: I will try and let you know. 

    Meanwhile I tried other device with my FPGA, and link did come up with the same startup routine. However, Transmit is still not working. Could you please look into my schematics, is there anything wrong I am doing? I tried to look into one of the debug guideline available only on TI website, and values are as recommended. Could you please double check and provide your comments? 


     

    BTW, why you want to force 100M, instead not use Auto-Neg ?

    Hardik: While starting up application it is required to have knowledge of link speed to allocate memory and for scheduling tasks to work incoming frames. In most of the cases, link speed is predefined. In short, to have more deterministic application with limited internal resources it is must in many applications to force link speed. 

    Thank you,

    Hardik 

  • Hi Hardik,


    On Forced 100M link, you tried DP83867 based FPGA with other device in 100M force mode and link is happending ? Correct.

    Now only issue you have is Transmit data from your FPGA/PHY does not go out properly to PC.

    I suspect your MAC interface is not tuned properly. Typically to isolate the issue, suggest you try following loopback:

    1. MAC loopback:
    2. Reverse loopback.

    Regards,
    Geet
  • Hi,

    I am closing this thread. Incase you need further help, kindly open new thread and provide reference to this thread.

    Regards,
    Geet