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DP83867IR: EEE(Energy Efficient Ethernet) with DP83867

Kai Nomiyama
Expert 5405 points
Part Number: DP83867IR

Hi Team,

I have a question about EEE with DP83867.

I described comment below so could you help that?

Problem

there is a unit that has EEE function(UNIT 1) and when a board DP838867 is mounted(BOARD 1) is connected to the "UNIT 1" with 10/100M, there is no problem but when "BOARD 1" is connected to the "UNIT 1" with 1000M, "BOARD 1" gets interrupt a lots and transmission is degraded.

when "UNIT 1" EEE is disabled, this interrupt is resolved.

Setting

Disabled: Driver LPI related registers.

Question

From hardware perspective, does DP83867 have any function to address EEE interrupt by register setting?

Thanks,

Kai

  • 0
    TI__Mastermind 23675 points
    Hi Kai,

    Are you bootstrapping RX_DV/CTRL to MODE 3?
    This is required bootstrap mode.

    Please see a similar post and resolution here: e2e.ti.com/.../556456
  • 0 in reply to Ross Pimentel
    TI__Expert 5405 points
    Hi Ross,

    Customer is investigating referring to the post you attached.
    I will let you know if I got a question from them.

    Regards,
    Kai
  • 0 in reply to Kai Nomiyama
    TI__Mastermind 23675 points
    Hi Kai,

    Yes, please keep us updated.
  • 0 in reply to Ross Pimentel
    TI__Expert 5405 points
    Hi Ross,

    I got additional questions so could you help below?

    ①4-Level strap pins
    Do they need to put all strap pins(pins described in DP83867IR datasheet page 46/47) to MODE 3?


    ②MODE 3
    Does "SET MODE 3" mean enable auto-negotiation?


    ③EEE
    Does PHY send LPI command to MAC when PHY supports EEE by PHY-self?

    Customer found PHY sends LPI command to MAC even if MAC EEE(CPU side) is disabled so they think this LPI command causes someting interruption and clear event.


    Regards,
    Kai
  • 0 in reply to Kai Nomiyama
    TI__Mastermind 23675 points
    Hi Kai,

    Only RX_DV must have MODE 3 strap (if not using the alternative method described below).
    None of the other bootstrap pins require MODE 3 strap.

    MODE 3 strap on RX_DV will enable auto-negotiation.

    The PHY will not send LPI commands when RX_DV is set to MODE 3 strap.

    If you cannot add MODE 3 strap on RX_DV, you can also use SMI (MDIO/MDC) method.
    You can configure register 0x0031, bit[7] to 0b0.
  • 0 in reply to Ross Pimentel
    TI__Expert 5405 points

    Hi Ross,

    I got update for this.

    They found there is no interruption following below prcedure.

    1. set 0x31 bit[7] to 0. (MODE 3)
    2. set 0x1F bit[14] to 1. (global software restart) ※1
    3. release LPI state in MAC side.　※2

    ※1: they found MAC re-enters LPI state when only #1 is done. It might LPI command from PHY doesn't affect by only write 0x31.
    ※2: After start-up, MAC has been already in LPI state before #1 procedure. Therefore need #3 procedure.

    From above results, could you help below questions?

    ■MODE 3 Auto Negotiation
    "Mode 3 strap enables auto-negotiation". Does it mean PHY disables/exits "EEE function" by auto-negotiation?

    Could you also shere if there are any materials shows how to work each mode1/2/3/4 straps?


    ■activate MODE 3 Auto Negotiation setting
    Is software restart(0x1F bit[14] to 1) needed for MODE 3 auto-negotiation?
    if there are any other ways, could you let me know since auto-negotiation re-run after global software restart?


    ■Reset function
    What is the difference between "IEEE software reset" and "Global software reset" and how to use these depending on?
    I can read "IEEE software reset" resets the IEEE-defined standard registers and "Global software reset" resets all the internal circuits in the PHY including IEEE-defined registers and all the extended registers.
    however, don't know how to distingusish these.

    Regards,
    Kai

  • 0 in reply to Kai Nomiyama
    TI__Mastermind 23675 points
    Hi Kai,

    The reason why we want you to strap two Mode 3 is for two reasons:
    1. To disable the non-functional EEE mode
    2. To enable auto-negotiation

    Auto-negotiation must be enabled for link to be established at 1Gbps speed. There is no forced mode standard for 1Gbps.
    This is why we want you to keep auto-negotiation enabled.

    In the datasheet under 'Strap Configuration' section it talks about how you strap for Mode 1, 2, 3 and 4.

    You need to implement a soft restart whenever doing register changes. Yes, bit[14] in register 0x1F is required to re-start auto-negotiation process.

    A soft reset (bit[14]) does not re-sample the bootstrap settings. It only clears the digital but does not clear your register configurations.
    A hard reset (bit[15]) is the same as using the RESET pin and will completely clear the device, including bootstraps and register settings.
  • 0 in reply to Ross Pimentel
    TI__Expert 5405 points
    Hi Ross,

    I have one more question.
    I add #4 as below. When LAN cable is removed, the LPI interrution is obserbed.

    1. set 0x31 bit[7] to 0. (MODE 3)
    2. set 0x1F bit[14] to 1. (global software restart) ※1
    3. release LPI state in MAC side.　※2
    (NEW)4: remove LAN cable. LPI interruption is obserbed.


    MAC_RX_LPI_Receive_Status register is "H" in CPU register so it seems PHY sends someting LPI command to CPU.
    ※at this time, DP83867 0x31 bit[7] is still 0.
    ※recover normal operation when LPI interruption is cleared at CPU side.


    They think if 0x31 bit[7] is 0 and do software reset to PHY, PHY doesn't send LPI command but it that understanding wrong?

    Regards,
    Kai
  • 0 in reply to Kai Nomiyama
    TI__Expert 5405 points
    Hi Ross,

    I know you are busy but I'm looking forward to your reply.

    Regards,
    Kai
  • 0 in reply to Kai Nomiyama
    TI__Mastermind 19780 points

    Hi Kai,

    Setting the bit in register 0x31 will disable EEE mode negotiation with the link partner.  After bit[7] in 0x31 is cleared, the link should be restarted by writing 0x1200 to register 0x0, or writing 0x4000 to register 0x1F to do software restart.

    If LPI is still occuring after 0x31 is set, it may be possible the customer is not accessing the extended registers(all registers with higher addresses than 0x1F) correctly.

    Please review the extended register space access methods in the datasheet DP83867.

    Best Regards,